E t h e r n e t M o d u l e

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

D29:28

R

RXFDB

0

Receive FIFO data available

 

 

 

 

Valid only when RXREGR (D27) = 1.

 

 

 

 

00

Full-word

 

 

 

 

01

One byte

 

 

 

 

10

Half-word

 

 

 

 

11 Three bytes; LENDIAN determines which

 

 

 

 

 

three

 

 

 

 

Must be used in conjunction with RXREGR. When

 

 

 

 

RXREGR is set to 1, RXFDB identifies how many

 

 

 

 

bytes are available in the Receive Data register.

 

 

 

 

 

D27

R

RXREGR

0

Receive register ready

 

 

 

 

Set to 1 when data is available to be read from the

 

 

 

 

FIFO Data register. When set active high, this bit

 

 

 

 

can cause an interrupt when the ERXREG bit is also

 

 

 

 

set (in the Ethernet General Control register).

 

 

 

 

RXREGR is never active when RXBR (D25) is set;

 

 

 

 

RXBR must be cleared to activate RXREGR.

 

 

 

 

 

D26

R

RXFIFOH

0

Receive FIFO half full

 

 

 

 

Set to 1 when the receive FIFO is at least half full

 

 

 

 

(>1024 bytes). When set active high, this bit can

 

 

 

 

cause an interrupt when the ERFIFOH bit is set (in

 

 

 

 

the Ethernet General Control register).

 

 

 

 

 

D25

R/C

RXBR

0

Receive buffer ready

 

 

 

 

Set to 1 when a new packet is available in the

 

 

 

 

receive FIFO. When set active high, this bit can

cause an interrupt when the ERXBR bit is also set (in the Ethernet General Control register).

RXBR indicates to the interrupt service routine (ISR) that the Receive Status register should be read. After reading that register, clear RXBR by writing a 1 to the RXBR position in this (Ethernet General Status) register. When RXBR is cleared, RXREGR and RXFIFOH become active.

Table 55: Ethernet General Status register bit definition

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Digi NS7520 manual Receive Fifo data available, Receive register ready, Receive Fifo half full, Receive buffer ready