G E N m o d u l e r e g i s t e r s

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

D28

R/W

BCLKD

0

BCLK output disable

 

 

 

 

0

BCLK output enabled

 

 

 

 

1 BCLK output forced to LOW state

 

 

 

 

Shuts down the operation of the BCLK signal.

 

 

 

 

Turning off the BCLK signal minimizes electro-

 

 

 

 

magnetic interference (EMI) when BCLK is not

 

 

 

 

required for an application.

 

 

 

 

 

D27:25

N/A

Reserved

N/A

N/A

 

 

 

 

 

D24

R/W

SWE

0

Software watchdog enable

 

 

 

 

Set to 1 to enable the watchdog timer circuit.The

 

 

 

 

watchdog timer can be configured, using SWRI, to

 

 

 

 

generate an interrupt or reset condition if and

 

 

 

 

when the watchdog timer expires. Once SWE is

 

 

 

 

set to 1, only a hardware reset sets the bit back

 

 

 

 

to 0.

 

 

 

 

 

D23:22

R/W

SWRI

0

Software watchdog reset/interrupt select

 

 

 

 

Controls the action that occurs when the

 

 

 

 

watchdog timer expires:

 

 

 

 

00

Software watchdog causes normal (IRQ)

 

 

 

 

 

interrupt

 

 

 

 

01

Software watchdog causes fast (FIRQ)

 

 

 

 

 

interrupt

 

 

 

 

10

Software watchdog causes reset

 

 

 

 

11

Reserved

 

 

 

 

 

D21:20

R/W

SWT

0

Software watchdog timeout (in seconds)

 

 

 

 

Controls the timeout period for the watchdog

 

 

 

 

timer. The timeout period is a function of FXTALE:

 

 

 

 

00

220/F

 

 

 

 

 

XTALE

 

 

 

 

01

222/FXTALE

 

 

 

 

10

224/FXTALE

 

 

 

 

11

225/F

 

 

 

 

 

XTALE

D19

N/A

Reserved

N/A

N/A

Table 24: System Control register bit definition

6 4

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

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Image 78
Digi NS7520 manual Bclk output disable, Software watchdog enable, Software watchdog reset/interrupt select