Digi NS7520 manual Ethernet Fifo Data register, Address FF80 0008 / FF80 000C secondary address

E t h e r n e t M o d u l e

Bits	Access	Mnemonic	Reset	Description
D15:10	R	RXPINS	0	ENDEC PHY status
				The logic state of the pins RXD2, RXD1, RXD3,
				RXER, and RXDV is read from this field. These pins
				are useful only with an ENDEC PHY, and monitor
				status signals on the PHY.
				When an MII PHY is used, these bits should be
				ignored.
				See Table 56 on page 167 for more information.
D09:00	N/A	Reserved	N/A	N/A

Table 55: Ethernet General Status register bit definition

Table 56 shows the relationship between the lower bits in the Ethernet General Status register and the NS7520 pins they monitor. The significance of each bit depends on the selected PHY and the wiring of the PHY to these pins.

Data bit NS7520 pin

D15RXD2

D13RXD1

D12RXD3

D11RXER

D10RXDV

Table 56: ENDEC status signal cross-reference

Ethernet FIFO Data register

Address: FF80 0008 / FF80 000C (secondary address)

The Ethernet FIFO Data register allows manual interface with the Ethernet FIFO, rather than using DMA support. This register is used primarily as a diagnostic tool.

Writing to the Ethernet FIFO Data register

Writing to the Ethernet FIFO Data register loads the transmit FIFO. This register can be written only when the TXREGE bit is set in the Ethernet General Status register, indicating that space is available in the transmit FIFO.

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