Digi NS7520 manual PLL Control register bit definition, Pllcnt, Sysclk frequency

							S Y S M o d u l e
MHz	A[8:7]	IS	A[6:5]	FS	A[4:0]	ND+1	PLL Settings reg	Notes
147.5	10	11	11	00	01011	1000000	0X0000019F

Notes:

1Digi guarantees that the NS7520B-1-C36 will work at all frequencies up to 36.9MHz.

2Digi guarantees that the NS7520B-1-C46 will work at all frequencies up to 46.1MHz.

3Digi guarantees that the Ns7520B-1-C55 will work at all frequencies up to 55.3MHz.

455.3MHz is the default frequency when address lines A[8:0] are not adjusted with pulldown resistors.

PLL Control register: Setting the PLL frequency with the PLL Control register

With this method, the PLL Settings register is configured by writing to the PLL Control register, FFB0 0008.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	Reserved				PLLCNT						Reserved
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							Reserved

Bits	Access	Mnemonic	Reset	Description
D31:28	N/A	Reserved	N/	N/A
D27:24	R/W	PLLCNT	0x9	SYS_CLK frequency
				Writing to this field affects the PLL frequency.
				See the discussion following this table.
D23:00	N/A	Reserved	N/A	N/A

Table 22: PLL Control register bit definition

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