Digi NS7520 manual System clock and reset, System clock pinout

P i n o u t d e t a i l t a b l e s a n d s i g n a l d e s c r i p t i o n s

System clock and reset

Symbol	Pin	I/O	OD	Description
XTALA1	K14	I		ARM/system oscillator circuit
XTALA2	K12	O
PLLVDD (1.5V)	L15	P		PLL clean power
PLLVSS	L12	P		PLL return
RESET_	A10	I		System reset

Table 10: System clock pinout

Signal descriptions

The NS7520 has three clock domains: System clock (SYSCLK)

Bit rate generation and programmable timer reference clock (XTALA1/2) System bus clock (BCLK)

The SYS module provides the NS7520 with these clocks, as well as system reset and backup resources.

Mnemonic	Signal	Description
XTALA1	Oscillator input	A standard parallel quartz crystal or crystal
XTALA2	Oscillator output	oscillator can be attached to these pins to provide
		the main input clock to the NS7520.
PLLVDD	Clean PLL power	Power and ground for PLL circuit.
PLLVSS	Connect directly to the
	GND plane
RESET_	System reset	Resets the NS7520 hardware.

Table 11: Clock generation and reset signal description

2 4 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6