Enable Transmit Data register ready interrupt | Digi NS7520 manual

				E t h e r n e t M o d u l e


Bits	Access	Mnemonic	Reset	Description

D19	R/W	ETXREG	0	Enable Transmit Data register ready interrupt
				Set to 1 to generate an interrupt when the TX FIFO
				is ready to accept data.

D18	R/W	ETFIFOH	0	Enable transmit data FIFO half empty interrupt
				Must be set to 1 to generate an interrupt when the
				TX FIFO is at least half empty (<256 bytes).

D17	R/W	ETXBC	0	Enable transmit buffer complete interrupt
				Set to 1 to generate an interrupt when the transmit
				packet transmission is complete.

D16	R/W	EFULLD	0	Enable full-duplex operation
				Set to 1 to allow the Ethernet TX and RX DMA
				operations to operate simultaneously. This bit must
				be set when the Ethernet link negotiation results in
				full-duplex mode.
				It is recommended that you limit transmit frames to
				512 bytes when full-duplex operation is enabled.

D15:14	R/W	MODE	0	Ethernet interface mode
				00 10/100 Mbps MII mode
				10 10 Mbps Level 1 ENDEC mode
				11 10 Mbps SEEQ ENDEC mode
				Identifies the type of Ethernet PHY attached to the
				NS7520.
				In ENDEC SEEQ mode, the LPBK pin is inverted
				before driving the MDC pin.
				In ENDEC Level 1 mode, the PDN signal is driven
				using an open-drain output driver.

D13	N/A	Reserved	N/A	Reads as zero.

D12	R/W	RXCINV	0	Invert the receive clock input
				Set to 1 only when the external Ethernet PHY
				generates a clock that is inverted in phase relative
				to what the MAC is expecting.

This bit is not required for most commercially available PHY devices.

Table 53: Ethernet General Control register bit definition

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Image 175

Digi NS7520 manual Enable Transmit Data register ready interrupt, Enable transmit data Fifo half empty interrupt

Contents

NS7520 Hardware Reference Page Part number/version 90000353D Release date March Page Contents A p t e r 4 B B u s M o d u l e A p t e r 7 M e m o r y C o n t r o l l e r M o d u l e A p t e r A p t e r 1 0 S e r i a l C o n t r o l l e r M o d u l e D e Who should read this guide About this guide Conventions used in this guide What’s in this guideTo read about See For Contact information Documentation updatesRelated documentation Customer supportPage About the NS7520 Key features and operating modes of the major NS7520 modules NS7520 Features O u t t h e N S 7 5 2 7 5 2 0 F e a t u r e s NS7520 overview NS7520 module block diagram Operating frequency Pinout and Packaging Symbol Min Nom Max NS7520 packaging dimensionsPackaging NS7520 pinout and dimensions NS7520 BGA layout Column Description Pinout detail tables and signal descriptions External bus Symbol Pin DescriptionSystem bus interface System bus interface pinout ADDR4 ADDR7ADDR6 ADDR5 Do not USE System bus interface signal description Signal descriptionsMnemonic Signal Description Chip select controller pinout Chip select controllerBusy Mnemonic Signal Chip select controller signal description Ethernet interface MAC pinout Ethernet interface MAC Ethernet interface MAC signal description CRS COL General-purpose I/O No connect pinsNo connect pins Serial Other Pin Serial channel Signal Description DSR RTS PORTC4 RXCB/RIB ResetPORTA3 Rxda DACK1 PORTA2 Dsra Amux Serial channel Other Description Gpio signalSerial signal Other signal Clock generation and reset signal description System clock and resetSystem clock pinout Bisten System mode test supportSystem mode and system reset pinout Plltst Jtag test ARM debugger ARM debugger signal descriptionJtag test pinout Trst termination GND Power supplyPower supply pinout Signal Pin Description Working with the CPU CPU performance ARM Thumb concept ARM ARM modeWorking with ARM exceptions ARM performance Exception priorities Summary of ARM exceptions Exception vector table Exception vector tableVector Description Address Detail of ARM exceptions Reset exceptionUndefined exception Abort exception SWI exception Firq exception IRQ exception Entering an exception Entering and exiting an exception software actionExiting an exception Abort P Reset UndefException entry/exit summary Exception entry/exit by exception type Firq and IRQ lines Hardware InterruptsInterrupt controller Interrupt sources W . d i g i . c o m Page BBus Module Module Master Slave BBus masters and slavesCycles and BBus arbitration BBus masters and slaves BBus address decoding Address decodingAddress range Module Page SYS Module Signal mnemonic Signal name Description Signal descriptionJtag support System clock generation NS7520 clock module ARM debugExternal oscillator vs. internal PLL circuit NS7520 clock module block diagram Using the external oscillator External oscillator mode hardware configuration PLL mode hardware configuration Using the PLL circuit PLL mode hardware configuration Bits Access Mnemonic Reset Description D3109 Reserved Setting the PLL frequencyPLL Settings register Setting the PLL frequency on bootup PLL Settings register bit definition PLL multiplier Bits Access Mnemonic Reset DescriptionMHz A87 A65 A40 ND+1 PLL Settings reg Output divider MHz A87 A65 A40 ND+1 PLL Settings reg Pllcnt PLL Control register bit definitionSysclk frequency MHz ND+1 PLL Settings register Reset circuit sources Address bit Name Description NS7520 bootstrap initialization GEN Module Address Register Module configurationGEN module address configuration GEN module hardware initialization General information GEN module registersSystem Control register Address FFB0 Software watchdog timeout in seconds Bclk output disableSoftware watchdog enable Software watchdog reset/interrupt select Enable access to internal chip registers in CPU Bus monitor enableUser mode Bus interface TEA/LAST configuration Bits Access Mnemonic ResetDescription Enable ARM CPU DMA module test mode DMA module reset CPU disableTA input synchronizer NS7520 revision ID Last reset caused by external resetSystem Status register System Status register bit definition Product ID defined by external resistor jumpers Last reset caused by watchdog timerLast reset caused by PLL update Last reset caused by software reset Address FFB0 000C Software Service registerTimer Control registers Software Service register bit definition Timer interrupt mode Timer Control registers bit definitionTimer enable Timer interrupt enable Timer clock source Timer prescalerInitial timer count Current timer count Timer Status registersTimer Status registers bit definition Timer interrupt pending Porta data direction Porta Configuration registerPorta mode configuration Porta register bit definition Porta data register Porta ConfigurationPorta configuration Adata IN/SER1DCD PORTA1 Gpio Gpio OUT SER1CTS DONE1OUT PORTA0 SER1SPISENABLEInputs Outputs Portc data direction Portc Configuration registerPortc mode Portc register bit definition Portc data register Portc configurationPortc configuration Cdata PORTC1 Gpio Gpio OUT LEVELIRQ1=CDIR1 PORTC0 LEVELIRQ0=CDIR0 PORTC30 Interrupts Address FFB0 0030 / 0034 Interrupt controller registers Interrupt Enable registers bit definition D01 Page Memory Controller Module About the MEM module Pin configurationMEM module pin configuration by memory type Mode A2714 A130 CSx Sdram Mode A2714 A130RAS CAS Address Mnemonic Register MEM module configurationSetting the chip select address range Memory controller register map Memory Space Refresh count value Memory Module Configuration registerEnable Dram refresh Mmcr bit definition Refresh cycle count Enable external address multiplexingEnable A27 output Rcyc AMUX2 A27 and A26 bit settingsEnable A26 output Enable A25 output Base address Chip Select Base Address registerChip Select Base Address register bit definition Base Peripheral page size Dram configuration modeDram address multiplexer select Force Bclk at end of memory cycle External TA configurationDram internal address multiplexer mode Burst memory cycle enable Eeprom Write-protect the chip selectValid bit Mask Address Chip Select Option Register aChip Select Option Register a bit definition Mask When DRSEL=1 and DMODE=2’b00 When DRSEL=0When DRSEL=1 and DMODE=2’b01 at full speed Port size When DRSEL=1 and DMODE=10Burst access size in beats Bsize WE Ctrl Read cycle modeWrite cycle mode OE Ctrl Chip Select Option Register B bit definition Chip Select Option Register B Sync Static memory Sram controller Sync Write Sync Read Single cycle read/write Async Read Burst cycles NS7520 Dram address multiplexing Using the internal multiplexer000 001 010 011 100 101 110 111 7 5 2 0 D R a M a d d r e s s m u l t i p l e x i n g NS7520 multiplexed address outputs Internal Dram multiplexing ModeDram Using the external multiplexer FP/EDO Dram controller Dram refresh FP Dram Write FP Dram Read Normal FP Dram bus cycles FP Dram burst cycles FP/EDO Dram burst cycles NS7520 Sdram interconnect X32 Sdram configurationX32 Sdram interconnect BA1 Bclk CLK VCC CKE X16 Sdram configurationBA1 BA0 Udqm NS7520 signal 16M Sdram signal 64M Sdram signalX16 Sdram interconnect CAS3 RAS CAS2 CAS1 CAS0 Bclk CLK VCC CKE X8 Sdram configurationsNS7520 signal 16M Sdram signal X8 Sdram interconnect Sdram A10/AP support Command Command definitionsSdram command definitions Mux mode X32 X16 Burst length Bsize configurationCAS latency Bcyc configuration Memory timing fields Sdram Address Field Value Sdram Mode registerSdram Mode register settings Full Sdram normal read Sdram read cycles Sdram burst read Sdram normal write Sdram write cycles Sdram burst write Example Peripheral page burst size Wait Bcyc Page DMA Module Fly-by operation transfers DMA module DMA fly-by transfers Memory-to-memory operation DMA buffer descriptor DMA buffer descriptor Fly-by mode Buffer descriptor bit definitions Buffer descriptor bit definitionsBit Description Buffer descriptor field definitions Buffer descriptor field definitionsField Description DMA channel assignments Channel Base address DMA channel peripheral Fly-by modeDMA channel assignments Address map DMA channel registersAddress Description Address Description DMA Control register Buffer Descriptor Pointer register Channel abort request DMA channel enableDMA operation mode DMA Control register bit definition Memory-to-memory mode Burst transfer enableBTE Channel request source REQ Destination address increment SincSource address increment Dinc Current DMA channel state shown in binary Data operand sizeCurrent DMA channel buffer descriptor index Normal completion interrupt pending DMA Status/Interrupt Enable registerDMA Status/Interrupt Enable register bit definition Error completion interrupt pending Buffer not ready interrupt enable Premature complete interrupt enableNormal completion interrupt enable Error completion interrupt enable Ethernet transmitter considerations External peripheral DMA support Ethernet receiver considerations Signal Description Signal descriptionExternal DMA configuration Memory-to-memory mode Hardware needed for external memory-to-memory DMA transfers DMA controller resetPage Ethernet Module Fifo Ethernet front-end EFE EFE transmit processing Transmit and receive FIFOsEFE receive processing DMA Receive buffer descriptor selection External CAM filtering MAC module MAC module block diagram Other modules in the diagram include EFE register map EFE configurationAddress Register Register description Mcfg MaxfSupp Test Erxregetxreg Erfifohetfifoh Erxbretxbc Ethernet General Control register Egcr bit definitionsAddress FF80 Erxetx Erxdmaetxdma Erxlngetxwm Erxshtefulld Erxbad Ethernet General Control register bit definition Receiver in interrupt service mode Enable transmit FifoEnable transmit DMA Do not set this bit when operating the Ethernet Enable full-duplex operation Enable Transmit Data register ready interruptEnable transmit data Fifo half empty interrupt Enable transmit buffer complete interrupt Insert transmit source address MAC software resetInvert the transmit clock input PSOS pNA buffer descriptors Mode field Output based on EFE CSR bit Endec mode and NS7520 pinsEndec control signal cross-reference External interface mode Ethernet General Status register bit definition Ethernet General Status register Egsr bit definitionsRxfdbrxskip Rxregrtxrege Rxfifohtxfifoh Rxbrtxbc Receive buffer ready Receive Fifo data availableReceive register ready Receive Fifo half full Transmit buffer complete Receive buffer skipTransmit register empty Transmit Fifo half empty Writing to the Ethernet Fifo Data register Endec status signal cross-referenceEthernet Fifo Data register Address FF80 0008 / FF80 000C secondary address Reading from the Ethernet Fifo Data register Fifo data FF80 Ethernet Transmit Status registerEthernet Fifo Data register bit definition Ethernet Transmit Status register bit definition Transmit abort late collision Packet transmitted OKBroadcast packet transmitted Multicast packet transmitted Transmit abort excessive collisions TxaedTransmit abort excessive deferral Txaec Transmit abort jumbo TxaurTransmit aborted underrun Txaj Txcrc Transmit CRC errorTxdef Transmit packet deferred Txcolc Ethernet Receive Status registerTransmit collision count Receive data violation event previously seen Ethernet Receive Status register bit definitionReceive buffer size in bytes Receive carrier event previously seen Receive multicast packet Receive packet has CRC errorReceive packet has dribble bit error Receive broadcast packet Receive packet is too long Receive packet has code violationReceive packet is too short Rover MAC Configuration RegisterReceive overflow MAC Configuration Register 1 bit definition RX flow control Receive enablePass ALL receive frames MAC Configuration Register 2 bit definition CRC enable Auto detect pad enableVlan pad enable PAD/CRC enable PAD operation Pad operation table Back-to-Back Inter-Packet-Gap register bit definition Back-to-Back Inter-Packet-Gap registerBack-to-back inter-packet-gap Non back-to-back inter-packet-gap part Non-Back-to-Back Inter-Packet-Gap registerAddress FF80 040C Non-Back-to-Back Inter-Packet-Gap register bit definition Retransmission maximum Collision Window/Collision Retry registerCollision Window/Collision Retry register bit definition Collision window Maximum Frame register bit definition Maximum Frame registerMaximum frame length PHY Support register bit assignment PHY Support register Address FF80 041C Enable Jabber protectionBit mode Test register Test pause Test backpressureShortcut pause quanta Clock select MII Management Configuration registerMII Management Configuration register bit definition Reset MII management Clks field Sysclk ratio MHz example Clks field settingsScani Scan increment single scan for read data Single scan for read data MII Management Command registerMII Management Command register bit definition Automatically scan for read data MII PHY register address MII Management Address registerMII Management Address register bit definition MII PHY device address MII write data MII Management Write Data registerAddress FF80 042C MII Management Write Data register bit definition MII Management Read Data register bit definition MII Management Read Data registerMII read data Automatically scan for read data in progress MII Management Indicators registerMII Management Indicators register bit definition Read data not valid Station Address registers Smii Status registerSmii Status register bit definition Station address octet Station Address RegisterStation Address Register 1 bit definition Station Address Register 2 bit definition OCTET5 Station Address Register 3 bit definitionOCTET3 OCTET4 Address FF80 05C0 Station Address Filter registerStation Address Filter register bit definition Address FF80 05D4 Register hash tableMulticast hash table entries and bit definitions Address FF80 05D0 HT3 bit definition Address FF80 05D8Address FF80 05DC HT2 bit definition Calculating hash table entries W . d i g i . c o m Page W . d i g i . c o m Page Serial Controller Module RTS, CTS, DTR, DSR, DCD, RI Supported features Bit-rate generator Serial port block diagram Serial protocols Uart mode SPI mode Terminology What’s being written Value Fifo managementTransmit Fifo interface Operating in Endian modes Receive Fifo interface Processor interrupts vs. DMA Using DMA Using processor interrupts Signals SPI master modeConfiguration SPI master transmitter SPI master receiver SPI slave mode Signals SPI slave receiver SPI slave transmitter SPI slave mode 0 and 1 two-byte transfer General-purpose I/O configurations Operating Mode Serial Port Maximum Rate ConfigurationSerial port performance N f i g u r a t i o n Serial Channel Control Register a Serial Channel registersSerial Channel 1, 2 Control Register a Address FFD0 0000 Number of stop bits Parity enableStick parity Even parity select General-purpose output 1/General-purpose Enable the transmitter with active CTSRemote loopback Local loopback Receiver interrupt condition Enable receive DMA requestsData terminal ready active Request-to-send active Transmitter interrupt condition Receiver interrupt enable bitsEnable transmit DMA requests Receiver interrupts Transmitter interrupts Transmitter interrupt enable bits Address FFD0 0004 Serial Channel 1, 2 Control Register BSerial Channel Control Register B bit definition Bitordr Enable receive character GAP timerSCC mode Rcgt Transmit encoding Enable active RTS only while transmittingReceive data encoding Differential Manchester 111. a 1 is Address FFD0 0008 Serial Channel 1, 2 Status Register a Character Match3 Serial Channel Status Register a bit definitionCharacter Match1 Character Match2 Cgap Buffer GAP timerCharacter GAP timer Bgap Current data set ready state Current ring indicator stateDCD Current data carrier detect state Receive parity error interrupt pending Receive framing error interrupt pendingReceive break interrupt pending Rrdy Receive overrun interrupt pendingReceive register ready interrupt pending Receive buffer closed interrupt pending Receive Fifo half-full interrupt pendingReceive Fifo full Change in CTS interrupt pending Change in DCD interrupt pendingChange in RI interrupt pending Change in DSR interrupt pending Transmit Fifo half-empty interrupt pending Transmit register empty interrupt pendingTransmit buffer closed interrupt pending Address FFD0 000C / 4C Serial Channel 1, 2 Bit-Rate registersTempty Receive clock source Bit-rate generator enableTiming mode Serial Channel Bit-Rate register bit definition Drive receive clock external Transmit clock sourceDrive transmit clock external BRG input clock ClkmuxTransmit clock invert Receive clock invert Tdcr If Dpll is not used and you are not usingIf Dpll is not used but you are using When Dpll is used in the application, Receive divide clock rate Rdcr Receiver internal clock source TicsTransmit internal clock source Rics Max baudrates with different clock sources With the 18.432MHz crystal using Xtale as the clock sourceNreg 16X @ 55.296MHz With the 18.432MHz crystal using Sysclk as the clock source Bit rate examples X1 mode X8 mode X16 modeSerial Channel 1, 2 Fifo registers Address FFD0 0010 Data Serial Channel 1, 2 Receive Buffer Gap TimerAddress FFD0 0014 Data Address FFD0 0018 Serial Channel 1, 2 Receive Character Gap TimerRegister diagram and bit assignment Serial Channel Receive Buffer Gap Timer bit definition CT value Serial Channel Receive Character Gap Timer bit definition Address FFD0 0020 Serial Channel 1,2 Receive Match registerSerial Channel 1, 2 Receive Match Mask register Address FFD0 001C / 5C RMMB3 Serial Channel Receive Match Mask register bit definitionRMMB1 RMMB2Page Electrical Characteristics Sym Parameter Conditions Min Typ Max Unit DC characteristicsRecommended operating conditions Recommended operating thermal conditions DC characteristics outputs Input/Output characteristicsPad pullup and pulldown characteristics DC characteristics inputs Internal pullup characteristics Maximum voltage ratings AC characteristicsAC electrical specifications Absolute maximum ratings MDC, MDIO, TXEN, TXER, TXD30 Estimated Signal Load pF Device loadsSystem loading details PORTA3, PORTA1, PORTC3, PORTC1 MDC, TXD30, TXER, TXEN, TDO Oscillator CharacteristicsSignal Derating ns/pF Output buffer derating by load capacitance NS7520 TimingSpecifications Timing Diagrams Reset timing parameters ResettimingNum Description Min Typ Max Units Sram timing parameters Sram timingNum Description Min Max Unit CS* controlled read wait = Sram read Sram burst read CS* controlled read wait = 0, Bcyc = CS controlled write internal and external, wait = Sram write Sram burst write OE* controlled read wait = Sram OE read Sram OE burst read WE* controlled write wait = Sram WE write Sram WE burst write Sdram timing parameters Sdram timing Sdram read, CAS latency = Sdram read Active Read Inhibit Prechg Bterm Sdram burst read Sdram burst read Sdram write Sdram write Sdram burst write Sdram burst write Sdram refresh Sdram load mode FP Dram timing parameters FP Dram timing Fast Page read FP Dram read Fast Page burst read FP Dram burst read Fast Page write FP Dram write Fast Page burst write FP Dram burst write Fast page refresh Rcyc = Fprefreshcycles CAS3 CAS2 CAS1 CAS0 RF1 RF2 RF3 RF4 RF5 RF8 Ethernet timing parameters Ethernet timing Ethernet cam timing Ethernet PHY timing Num Description Min Max Units Jtag arm ice timing diagramJtag timing Jtag arm ice timing parameters Jtag bscan timing parameters Jtag bscan timing diagram External DMA timing parameters External DMA timing Fly-by external DMA Memory-to-memory external DMA 2T SYS Serial internal timing characteristicsSerial external timing characteristics Serial internal/external timing Synchronous serial external clock Synchronous serial internal clock Gpio timing Gpio timing diagramGpio timing parameters Page Index CPU Non-Back-to-BackInter-Packet-Gap register FP Dram Portc NET+ARM PORTC0 Receiver interrupts 229 transmitter interrupts Undefined exception 32 Page