M e m o r y C o n t r o l l e r M o d u l e

from address instead of chip select. The NS7520 provides the address signals during the earliest part of each memory cycle. The CS0OE_ and CS0WE_ signals are connected to the OE_ and WE_ input for the CS0 peripheral.

Chip Select Base Address register

Address: FFC0 0010/20/30/40/50

The Chip Select Base Address register defines the base starting address for the chip select.

Note: The V bit is set to 1 on hardware reset for chip select 0 only.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BASE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BASE

 

PGSIZE

DMODE

 

DMUX

EXTTA

DMUX

IDLE

DR

BURST

WP

V

 

 

 

 

 

 

 

 

 

S

 

M

 

SEL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

D31:12

R/W

BASE

0

Base address

 

 

 

 

Determines the physical base address of

 

 

 

 

the memory peripheral chip select. This

 

 

 

 

20-bit field represents the 20 most

 

 

 

 

significant bits of the physical address.

To derive the BASE field from a 32-bit physical address, remove the three least significant digits; for example, for a physical address of ’h00200000, the BASE field is set to ’h00200.

When accessing a static memory device, the maximum value of the base address is 0x03000000.

See "Setting the chip select address range" on page 88 for more information.

Table 37: Chip Select Base Address register bit definition

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Digi NS7520 manual Chip Select Base Address register bit definition, Base address