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Digi NS7520 manual A27 and A26 bit settings, Enable A26 output, Enable A25 output, AMUX2

Models: NS7520

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Bits	Access	Mnemonic	Reset	Description

D18	R/W	A[26]	0	Enable A26 output
				0 CS0WE_ is driven out the A26 pin
				1 The A26 signal is driven out the A26
				pin.
				The bit settings determine how the NS7520
				uses this signal. See "A27 and A26 bit
				settings" on page 92 for more information.

D17	R/W	A25	1	Enable A25 output
				Always set to 0; used for address bit 25.

D16	R/W	AMUX2	0	Internal/External/RAS/CAS mux
				0 Normal operation
				1 Drive the DRAM MUX control out
				PORTA2, regardless of the AMUX and
				DMUXS settings
				Used to drive the DRAM RAS/CAS address
				multiplexing control signal out the PORTA2
				pin, regardless of the AMUX setting.
				When set to 1, the memory controller drives
				the DRAM RAS/CAS address multiplexing
				control signal out the PORTA2 pin, for an
				external address multiplexer to use for
				DRAM RAS/CAS address multiplexing
				control.

D15:00	N/A	Reserved	N/A	N/A

Table 36: MMCR bit definition

A27 and A26 bit settings

The A27 bit setting determines how the A27 signal is used by the NS7520. CS0OE_ is generated by an internal logical AND of the CS0_ and OE_ signals. The CS0OE_ signal goes active low when both CS0_ and OE_ are active low.

The A26 bit setting determines how the A26 signal is used by the NS7520. The CS0WE_ signal is generated by an internal logical AND of the CS0_ and WE_ signals. the CS0WE_ signal goes active low when both CS0_ and WE_ are active low.

When enabled, these signals maximize the read access timing for external memory peripherals attached to CS0. When using CS0OE_, the CS0 peripheral’s chip select input is attached to GND, and the read-access time for that peripheral is referenced

9 2	N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

Image 106

Digi NS7520 manual A27 and A26 bit settings, Enable A26 output, Enable A25 output, AMUX2, Internal/External/RAS/CAS mux

Contents

NS7520 Hardware Reference Page Part number/version 90000353D Release date March Page Contents A p t e r 4 B B u s M o d u l e A p t e r 7 M e m o r y C o n t r o l l e r M o d u l e A p t e r A p t e r 1 0 S e r i a l C o n t r o l l e r M o d u l e D e About this guide Who should read this guideConventions used in this guide What’s in this guideTo read about See Customer support Documentation updatesRelated documentation For Contact informationPage About the NS7520 NS7520 Features Key features and operating modes of the major NS7520 modulesO u t t h e N S 7 5 2 7 5 2 0 F e a t u r e s NS7520 module block diagram NS7520 overviewOperating frequency Pinout and Packaging Symbol Min Nom Max NS7520 packaging dimensionsPackaging NS7520 pinout and dimensions NS7520 BGA layout Pinout detail tables and signal descriptions Column DescriptionSystem bus interface pinout Symbol Pin DescriptionSystem bus interface External busADDR5 ADDR7ADDR6 ADDR4Do not USE System bus interface signal description Signal descriptionsMnemonic Signal Description Chip select controller pinout Chip select controllerBusy Chip select controller signal description Mnemonic SignalEthernet interface MAC Ethernet interface MAC pinoutEthernet interface MAC signal description COL CRSSerial Other Pin Serial channel Signal Description No connect pinsNo connect pins General-purpose I/OPORTA2 Dsra Amux RTS PORTC4 RXCB/RIB ResetPORTA3 Rxda DACK1 DSROther signal Gpio signalSerial signal Serial channel Other DescriptionClock generation and reset signal description System clock and resetSystem clock pinout Plltst System mode test supportSystem mode and system reset pinout BistenJtag test ARM debugger ARM debugger signal descriptionJtag test pinout Trst termination Signal Pin Description Power supplyPower supply pinout GNDWorking with the CPU ARM Thumb concept CPU performanceARM performance ARM modeWorking with ARM exceptions ARMSummary of ARM exceptions Exception prioritiesException vector table Exception vector tableVector Description Address Detail of ARM exceptions Reset exceptionUndefined exception SWI exception Abort exceptionIRQ exception Firq exceptionEntering an exception Entering and exiting an exception software actionExiting an exception Exception entry/exit by exception type Reset UndefException entry/exit summary Abort PFirq and IRQ lines Hardware InterruptsInterrupt controller Interrupt sources W . d i g i . c o m Page BBus Module BBus masters and slaves BBus masters and slavesCycles and BBus arbitration Module Master SlaveBBus address decoding Address decodingAddress range Module Page SYS Module Signal mnemonic Signal name Description Signal descriptionJtag support System clock generation NS7520 clock module ARM debugExternal oscillator vs. internal PLL circuit Using the external oscillator NS7520 clock module block diagramExternal oscillator mode hardware configuration Using the PLL circuit PLL mode hardware configurationPLL mode hardware configuration PLL Settings register bit definition Setting the PLL frequencyPLL Settings register Setting the PLL frequency on bootup Bits Access Mnemonic Reset Description D3109 ReservedOutput divider Bits Access Mnemonic Reset DescriptionMHz A87 A65 A40 ND+1 PLL Settings reg PLL multiplierMHz A87 A65 A40 ND+1 PLL Settings reg Pllcnt PLL Control register bit definitionSysclk frequency ND+1 PLL Settings register MHzReset circuit sources NS7520 bootstrap initialization Address bit Name DescriptionGEN Module GEN module hardware initialization Module configurationGEN module address configuration Address RegisterAddress FFB0 GEN module registersSystem Control register General informationSoftware watchdog reset/interrupt select Bclk output disableSoftware watchdog enable Software watchdog timeout in secondsEnable access to internal chip registers in CPU Bus monitor enableUser mode DMA module test mode Bits Access Mnemonic ResetDescription Enable ARM CPU Bus interface TEA/LAST configurationDMA module reset CPU disableTA input synchronizer System Status register bit definition Last reset caused by external resetSystem Status register NS7520 revision IDLast reset caused by software reset Last reset caused by watchdog timerLast reset caused by PLL update Product ID defined by external resistor jumpersSoftware Service register bit definition Software Service registerTimer Control registers Address FFB0 000CTimer interrupt enable Timer Control registers bit definitionTimer enable Timer interrupt modeTimer clock source Timer prescalerInitial timer count Timer interrupt pending Timer Status registersTimer Status registers bit definition Current timer countPorta register bit definition Porta Configuration registerPorta mode configuration Porta data directionAdata Porta ConfigurationPorta configuration Porta data registerOutputs PORTA1 Gpio Gpio OUT SER1CTS DONE1OUT PORTA0 SER1SPISENABLEInputs IN/SER1DCDPortc register bit definition Portc Configuration registerPortc mode Portc data directionCdata Portc configurationPortc configuration Portc data registerPORTC1 Gpio Gpio OUT LEVELIRQ1=CDIR1 PORTC0 LEVELIRQ0=CDIR0 Interrupts PORTC30Interrupt controller registers Address FFB0 0030 / 0034Interrupt Enable registers bit definition D01 Page Memory Controller Module Mode A2714 A130 CSx Pin configurationMEM module pin configuration by memory type About the MEM moduleSdram Mode A2714 A130RAS CAS Memory controller register map MEM module configurationSetting the chip select address range Address Mnemonic RegisterMemory Space Mmcr bit definition Memory Module Configuration registerEnable Dram refresh Refresh count valueRcyc Enable external address multiplexingEnable A27 output Refresh cycle countEnable A25 output A27 and A26 bit settingsEnable A26 output AMUX2Base Chip Select Base Address registerChip Select Base Address register bit definition Base addressPeripheral page size Dram configuration modeDram address multiplexer select Burst memory cycle enable External TA configurationDram internal address multiplexer mode Force Bclk at end of memory cycleEeprom Write-protect the chip selectValid bit Mask Chip Select Option Register aChip Select Option Register a bit definition Mask AddressWhen DRSEL=1 and DMODE=2’b00 When DRSEL=0When DRSEL=1 and DMODE=2’b01 at full speed Bsize When DRSEL=1 and DMODE=10Burst access size in beats Port sizeOE Ctrl Read cycle modeWrite cycle mode WE CtrlChip Select Option Register B Chip Select Option Register B bit definitionStatic memory Sram controller SyncSingle cycle read/write Sync Write Sync ReadBurst cycles Async ReadNS7520 Dram address multiplexing Using the internal multiplexer000 001 010 011 100 101 110 111 7 5 2 0 D R a M a d d r e s s m u l t i p l e x i n g NS7520 multiplexed address outputs Internal Dram multiplexing ModeDram Using the external multiplexer Dram refresh FP/EDO Dram controllerNormal FP Dram bus cycles FP Dram Write FP Dram ReadFP/EDO Dram burst cycles FP Dram burst cyclesNS7520 Sdram interconnect X32 Sdram configurationX32 Sdram interconnect BA0 X16 Sdram configurationBA1 BA1 Bclk CLK VCC CKECAS3 RAS CAS2 CAS1 CAS0 NS7520 signal 16M Sdram signal 64M Sdram signalX16 Sdram interconnect UdqmX8 Sdram interconnect X8 Sdram configurationsNS7520 signal 16M Sdram signal Bclk CLK VCC CKESdram A10/AP support Mux mode X32 X16 Command definitionsSdram command definitions CommandMemory timing fields Sdram Bsize configurationCAS latency Bcyc configuration Burst lengthFull Sdram Mode registerSdram Mode register settings Address Field ValueSdram read cycles Sdram normal readSdram burst read Sdram write cycles Sdram normal writeSdram burst write Peripheral page burst size ExampleWait Bcyc Page DMA Module DMA module Fly-by operation transfersMemory-to-memory operation DMA fly-by transfersDMA buffer descriptor Fly-by mode DMA buffer descriptorBuffer descriptor bit definitions Buffer descriptor bit definitionsBit Description Buffer descriptor field definitions Buffer descriptor field definitionsField Description DMA channel assignments Channel Base address DMA channel peripheral Fly-by modeDMA channel assignments Address map DMA channel registersAddress Description Address Description Buffer Descriptor Pointer register DMA Control registerDMA Control register bit definition DMA channel enableDMA operation mode Channel abort requestMemory-to-memory mode Burst transfer enableBTE REQ Channel request sourceDinc SincSource address increment Destination address incrementCurrent DMA channel state shown in binary Data operand sizeCurrent DMA channel buffer descriptor index Error completion interrupt pending DMA Status/Interrupt Enable registerDMA Status/Interrupt Enable register bit definition Normal completion interrupt pendingError completion interrupt enable Premature complete interrupt enableNormal completion interrupt enable Buffer not ready interrupt enableEthernet transmitter considerations Ethernet receiver considerations External peripheral DMA supportMemory-to-memory mode Signal descriptionExternal DMA configuration Signal DescriptionDMA controller reset Hardware needed for external memory-to-memory DMA transfersPage Ethernet Module Ethernet front-end EFE FifoEFE transmit processing Transmit and receive FIFOsEFE receive processing Receive buffer descriptor selection DMAExternal CAM filtering MAC module block diagram MAC moduleOther modules in the diagram include EFE register map EFE configurationAddress Register Register description Test MaxfSupp McfgErxetx Erxdmaetxdma Erxlngetxwm Erxshtefulld Erxbad Ethernet General Control register Egcr bit definitionsAddress FF80 Erxregetxreg Erfifohetfifoh ErxbretxbcEthernet General Control register bit definition Do not set this bit when operating the Ethernet Enable transmit FifoEnable transmit DMA Receiver in interrupt service modeEnable transmit buffer complete interrupt Enable Transmit Data register ready interruptEnable transmit data Fifo half empty interrupt Enable full-duplex operationPSOS pNA buffer descriptors MAC software resetInvert the transmit clock input Insert transmit source addressExternal interface mode Endec mode and NS7520 pinsEndec control signal cross-reference Mode field Output based on EFE CSR bitEthernet General Status register bit definition Ethernet General Status register Egsr bit definitionsRxfdbrxskip Rxregrtxrege Rxfifohtxfifoh Rxbrtxbc Receive Fifo half full Receive Fifo data availableReceive register ready Receive buffer readyTransmit Fifo half empty Receive buffer skipTransmit register empty Transmit buffer completeAddress FF80 0008 / FF80 000C secondary address Endec status signal cross-referenceEthernet Fifo Data register Writing to the Ethernet Fifo Data registerReading from the Ethernet Fifo Data register Ethernet Transmit Status register bit definition Ethernet Transmit Status registerEthernet Fifo Data register bit definition Fifo data FF80Multicast packet transmitted Packet transmitted OKBroadcast packet transmitted Transmit abort late collisionTxaec TxaedTransmit abort excessive deferral Transmit abort excessive collisionsTxaj TxaurTransmit aborted underrun Transmit abort jumboTransmit packet deferred Transmit CRC errorTxdef TxcrcTxcolc Ethernet Receive Status registerTransmit collision count Receive carrier event previously seen Ethernet Receive Status register bit definitionReceive buffer size in bytes Receive data violation event previously seenReceive broadcast packet Receive packet has CRC errorReceive packet has dribble bit error Receive multicast packetReceive packet is too long Receive packet has code violationReceive packet is too short Rover MAC Configuration RegisterReceive overflow MAC Configuration Register 1 bit definition RX flow control Receive enablePass ALL receive frames MAC Configuration Register 2 bit definition PAD/CRC enable Auto detect pad enableVlan pad enable CRC enablePad operation table PAD operationBack-to-Back Inter-Packet-Gap register bit definition Back-to-Back Inter-Packet-Gap registerBack-to-back inter-packet-gap Non-Back-to-Back Inter-Packet-Gap register bit definition Non-Back-to-Back Inter-Packet-Gap registerAddress FF80 040C Non back-to-back inter-packet-gap partCollision window Collision Window/Collision Retry registerCollision Window/Collision Retry register bit definition Retransmission maximumMaximum Frame register bit definition Maximum Frame registerMaximum frame length PHY Support register PHY Support register bit assignmentTest register Enable Jabber protectionBit mode Address FF80 041CTest pause Test backpressureShortcut pause quanta Reset MII management MII Management Configuration registerMII Management Configuration register bit definition Clock selectScan increment single scan for read data Clks field settingsScani Clks field Sysclk ratio MHz exampleAutomatically scan for read data MII Management Command registerMII Management Command register bit definition Single scan for read dataMII PHY device address MII Management Address registerMII Management Address register bit definition MII PHY register addressMII Management Write Data register bit definition MII Management Write Data registerAddress FF80 042C MII write dataMII Management Read Data register bit definition MII Management Read Data registerMII read data Read data not valid MII Management Indicators registerMII Management Indicators register bit definition Automatically scan for read data in progressStation Address registers Smii Status registerSmii Status register bit definition Station Address Register 2 bit definition Station Address RegisterStation Address Register 1 bit definition Station address octetOCTET4 Station Address Register 3 bit definitionOCTET3 OCTET5Address FF80 05C0 Station Address Filter registerStation Address Filter register bit definition Address FF80 05D0 Register hash tableMulticast hash table entries and bit definitions Address FF80 05D4HT2 bit definition Address FF80 05D8Address FF80 05DC HT3 bit definitionCalculating hash table entries W . d i g i . c o m Page W . d i g i . c o m Page Serial Controller Module Supported features RTS, CTS, DTR, DSR, DCD, RISerial port block diagram Bit-rate generatorUart mode Serial protocolsSPI mode Operating in Endian modes Fifo managementTransmit Fifo interface Terminology What’s being written ValueProcessor interrupts vs. DMA Receive Fifo interfaceUsing processor interrupts Using DMASignals SPI master modeConfiguration SPI master transmitter SPI slave mode SPI master receiverSignals SPI slave transmitter SPI slave receiverGeneral-purpose I/O configurations SPI slave mode 0 and 1 two-byte transferOperating Mode Serial Port Maximum Rate ConfigurationSerial port performance N f i g u r a t i o n Address FFD0 0000 Serial Channel registersSerial Channel 1, 2 Control Register a Serial Channel Control Register aEven parity select Parity enableStick parity Number of stop bitsLocal loopback Enable the transmitter with active CTSRemote loopback General-purpose output 1/General-purposeRequest-to-send active Enable receive DMA requestsData terminal ready active Receiver interrupt conditionReceiver interrupts Receiver interrupt enable bitsEnable transmit DMA requests Transmitter interrupt conditionTransmitter interrupt enable bits Transmitter interruptsAddress FFD0 0004 Serial Channel 1, 2 Control Register BSerial Channel Control Register B bit definition Rcgt Enable receive character GAP timerSCC mode BitordrTransmit encoding Enable active RTS only while transmittingReceive data encoding Differential Manchester 111. a 1 is Serial Channel 1, 2 Status Register a Address FFD0 0008Character Match2 Serial Channel Status Register a bit definitionCharacter Match1 Character Match3Bgap Buffer GAP timerCharacter GAP timer CgapCurrent data carrier detect state Current ring indicator stateDCD Current data set ready stateReceive parity error interrupt pending Receive framing error interrupt pendingReceive break interrupt pending Rrdy Receive overrun interrupt pendingReceive register ready interrupt pending Receive buffer closed interrupt pending Receive Fifo half-full interrupt pendingReceive Fifo full Change in DSR interrupt pending Change in DCD interrupt pendingChange in RI interrupt pending Change in CTS interrupt pendingTransmit Fifo half-empty interrupt pending Transmit register empty interrupt pendingTransmit buffer closed interrupt pending Address FFD0 000C / 4C Serial Channel 1, 2 Bit-Rate registersTempty Serial Channel Bit-Rate register bit definition Bit-rate generator enableTiming mode Receive clock sourceDrive receive clock external Transmit clock sourceDrive transmit clock external BRG input clock ClkmuxTransmit clock invert Receive clock invert When Dpll is used in the application, If Dpll is not used and you are not usingIf Dpll is not used but you are using TdcrRdcr Receive divide clock rateRics TicsTransmit internal clock source Receiver internal clock sourceMax baudrates with different clock sources With the 18.432MHz crystal using Xtale as the clock sourceNreg With the 18.432MHz crystal using Sysclk as the clock source 16X @ 55.296MHzAddress FFD0 0010 X1 mode X8 mode X16 modeSerial Channel 1, 2 Fifo registers Bit rate examplesData Serial Channel 1, 2 Receive Buffer Gap TimerAddress FFD0 0014 DataSerial Channel Receive Buffer Gap Timer bit definition Serial Channel 1, 2 Receive Character Gap TimerRegister diagram and bit assignment Address FFD0 0018Serial Channel Receive Character Gap Timer bit definition CT valueAddress FFD0 001C / 5C Serial Channel 1,2 Receive Match registerSerial Channel 1, 2 Receive Match Mask register Address FFD0 0020RMMB2 Serial Channel Receive Match Mask register bit definitionRMMB1 RMMB3Page Electrical Characteristics Recommended operating thermal conditions DC characteristicsRecommended operating conditions Sym Parameter Conditions Min Typ Max UnitDC characteristics inputs Input/Output characteristicsPad pullup and pulldown characteristics DC characteristics outputsInternal pullup characteristics Absolute maximum ratings AC characteristicsAC electrical specifications Maximum voltage ratingsPORTA3, PORTA1, PORTC3, PORTC1 Estimated Signal Load pF Device loadsSystem loading details MDC, MDIO, TXEN, TXER, TXD30Output buffer derating by load capacitance Oscillator CharacteristicsSignal Derating ns/pF MDC, TXD30, TXER, TXEN, TDONS7520 Timing Diagrams TimingSpecificationsReset timing parameters ResettimingNum Description Min Typ Max Units Sram timing parameters Sram timingNum Description Min Max Unit Sram read CS* controlled read wait =Sram burst read CS* controlled read wait = 0, Bcyc = Sram write CS controlled write internal and external, wait =Sram burst write Sram OE read OE* controlled read wait =Sram OE burst read Sram WE write WE* controlled write wait =Sram WE burst write Sdram timing Sdram timing parametersSdram read Sdram read, CAS latency =Active Read Inhibit Prechg Bterm Sdram burst read Sdram burst read Sdram write Sdram writeSdram burst write Sdram burst writeSdram load mode Sdram refreshFP Dram timing FP Dram timing parametersFP Dram read Fast Page readFP Dram burst read Fast Page burst readFP Dram write Fast Page writeFP Dram burst write Fast Page burst writeFprefreshcycles Fast page refresh Rcyc =CAS3 CAS2 CAS1 CAS0 RF1 RF2 RF3 RF4 RF5 RF8 Ethernet timing Ethernet timing parametersEthernet PHY timing Ethernet cam timingJtag arm ice timing parameters Jtag arm ice timing diagramJtag timing Num Description Min Max UnitsJtag bscan timing diagram Jtag bscan timing parametersExternal DMA timing External DMA timing parametersFly-by external DMA Memory-to-memory external DMA Serial internal/external timing Serial internal timing characteristicsSerial external timing characteristics 2T SYSSynchronous serial internal clock Synchronous serial external clockGpio timing Gpio timing diagramGpio timing parameters Page Index CPU Non-Back-to-BackInter-Packet-Gap register FP Dram Portc NET+ARM PORTC0 Receiver interrupts 229 transmitter interrupts Undefined exception 32 Page