Digi NS7520 manual Chip select controller signal description, Mnemonic Signal

				P i n o u t a n d P a c k a g i n g
Symbol	Pin	I/O	OD	Description
CS0_	D5	O	4	Chip select (boot select)
CAS3_	A1	O	4	FP/EDO DRAM column strobe
				D31:D24/SDRAM RAS_
CAS2_	C4	O	4	FP/EDO DRAM column strobe
				D23:D16/SDRAM CAS_
CAS1_	B3	O	4	FP/EDO DRAM column strobe
				D15:D08/SDRAM WE_
CAS0_	A2	O	4	FP/EDO DRAM column strobe
				D07:D00/SDRAM A10(AP)
WE_	C6	O	4	Write enable for NCC Ctrl’d cycles
OE_	B6	O	4	Output enable for NCC Ctrl’d cycles

Table 4: Chip select controller pinout

Signal descriptions

Mnemonic	Signal
CS0_	Chip select 0
CS1_	Chip select 1
CS2_	Chip select 2
CS3_	Chip select 3
CS4_	Chip select 4

Description

Unique chip select outputs supported by the NS7520. Each chip select can be configured to decode a portion of the available address space and can address a maximum of 256 Mbytes of address space. The chip selects are configured using registers in the memory module.

A chip select signal is driven low to indicate the end of the current memory cycle. For FP/EDO DRAM, these signals provide the RAS signal.

Table 5: Chip select controller signal description

w w w . d i g i . c o m 1 7