D M A M o d u l e

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

D17:16

R/W

SIZE

0

Data operand size

 

 

 

 

00

32 bit

 

 

 

 

01

16 bit

 

 

 

 

10

8 bit

 

 

 

 

11

Reserved

 

 

 

 

Used to define the size of each DMA transaction

 

 

 

 

when the DMA controller is configured for external

 

 

 

 

request mode (DMA channel 3 only) or memory-to-

 

 

 

 

memory DMA mode.

 

 

 

 

 

D15:10

R

STATE

0

Current DMA channel state (shown in binary)

 

 

 

 

000000

— IDLE

 

 

 

 

000001

— Load source buffer address

 

 

 

 

000100

— Load destination buffer address

 

 

 

 

001000

— First operand

 

 

 

 

010000

Memory-to-memory second operand

 

 

 

 

100000

— Update buffer description

 

 

 

 

Describes the current state of the DMA controller

 

 

 

 

state machine.

 

 

 

 

 

D09:00

R

INDEX

0

Current DMA channel buffer descriptor index

 

 

 

 

Identifies the DMA controller’s current byte offset

 

 

 

 

pointer relative to the DMA buffer descriptor

 

 

 

 

pointer.

 

 

 

 

 

 

 

 

Table 50: DMA Control register bit definition

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Image 155
Digi NS7520 Data operand size, Current DMA channel state shown in binary, Current DMA channel buffer descriptor index