E l e c t r i c a l C h a r a c t e r i s t i c s

FP DRAM burst write

Fast Page burst write

 

T1

TW

T2

TW

T2

BCLK

 

 

 

 

 

TA* (Note-4)

 

 

30

30

 

 

 

 

 

 

TEA*/LAST (Note-4)

 

 

 

 

 

 

36

 

 

 

 

BE[3:0]*

Note-2

 

 

 

 

Non-muxed address

6

 

 

 

 

 

 

 

 

 

Muxed address

35

 

 

 

 

 

 

 

 

 

writeD[31:0]

 

9

 

 

 

 

 

 

 

 

WE*

 

29

 

 

 

 

 

 

 

 

RAS[4:0]*

 

27

 

 

 

 

 

 

 

 

CAS[3:0]*

Note-3

 

43

43

43

 

 

 

 

PortC3/AMUX

 

37

 

 

 

 

 

 

 

 

RW*

12

 

 

 

 

 

 

 

 

 

TW

T2

TW

T2

31

27

Note-1

T1

31

 

36

 

13

 

29

 

37

 

Notes:

1If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock pulses are required for DMA context switching.

2Port size determines which byte enable signals are active:

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

3Port size determines which CAS signals are active:

8-bit port = CAS3*

16-bit port = CAS[3:2]

32-bit port = CAS[3:0]

4The TA* and TEA*/LAST signals are for reference only.

5The BCYC field should never be set to 00.

w w w . d i g i . c o m

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Digi NS7520 manual FP Dram burst write, Fast Page burst write