Digi NS7520 manual Sdram burst read

M e m o r y C o n t r o l l e r M o d u l e

read	nop	nop	nop	bstop	inhibit
BCLK
TS_
RW_
BE[3:0]
D[31:0]
CS[7:0]_		One Valid Per Cy cle

CAS3_(RAS_) CAS2_(CAS_) CAS1_(WE_) A[13:0]

AMUX

TA_ {output}

TEA_(LAST_) {output}

TA_ {input}

TEA_(LAST_) {input}

Figure 12: SDRAM burst read

The precharge command is issued, when necessary, during the T1 phase of a normal or burst read cycle. The precharge command is issued only when the row selection for the NS7520 has changed since the last access. Each chip select maintains a 14-bit register identifying the last row accessed. Additional clock cycles are inserted between the precharge command and the active command, depending on the WAIT configuration.

The active command is always issued after the precharge command, and selects a newly activated row address. Additional clock cycles are inserted between the active command and the read command, depending on the WAIT configuration.

The read command is issued in either the T1 or TW states, depending on whether a precharge command was required. The read command selects the starting column address for the current burst read operation. Additional

w w w . d i g i . c o m 1 2 1