Digi NS7520 manual Receive packet has code violation, Receive packet is too long

				E t h e r n e t M o d u l e
Bits	Access	Mnemonic	Reset	Description
D08	R	RXCV	0	Receive packet has code violation
				Set to 1 to indicate that the Ethernet PHY asserted
				the RXER signal during the data phase of this
				frame. RXCV indicates that the PHY encountered
				invalid receive codes while receiving the data.
				When this bit is set, the RXREGR and RXFIFOH bits
				in the Ethernet General Status register remain
				inactive. The bad receive packet is flushed
				immediately from the FIFO.
D07	R	RXLNG	0	Receive packet is too long
				Set to 1 to indicate that the next packet in the
				receive FIFO is longer than 1518 bits. A long
				packet is accepted only when the ERXLNG bit is
				set in the Ethernet General Control register.
				When this bit is set, the RXREGR and RXFIFOH bits
				in the Ethernet General Status register remain
				inactive. The bad receive packet is flushed
				immediately from the FIFO.
D06	R	RXSHT	0	Receive packet is too short
				Set to 1 to indicate that the next packet in the

receive FIFO is smaller than 64 bytes. A short packet is accepted only when the ERXSHT bit is set in the Ethernet General Control register.

When this bit is set, the RXREGR and RXFIFOH bits in the Ethernet General Status register remain inactive. The bad receive packet is flushed immediately from the FIFO.

Table 59: Ethernet Receive Status register bit definition

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