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Digi NS7520 manual Memory Space

Models: NS7520

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M e m o r y C o n t r o l l e r M o d u l e

The BASE field in the Chip Select Base Address register defines the starting address of the chip select address space. The MASK field identifies those address bits, from A[31:12], that are used in the address decoding function.

A 1 in the MASK field indicates that the associated address bit is to be used in the decoding process.

A 0 in the MASK field indicates that the associated address is to be ignored in the address decoding process.

Note: When accessing a static memory device, the maximum value of the base address is 0x03000000.

To determine whether a BBus address is associated with a peripheral chip select, apply the following Boolean equation (chip select decode is TRUE when):

(({MASK,000} & 32-bit logical address) = = ({BASE,000} & {MASK,000}))

{MASK,000} is the MASK field concatenated with three nibbles of 0. {BASE,000} is the BASE field concatenated with three nibbles of 0.

&is the logical AND function.

==is the equal to operator.

The NS7520 supports only 28 address bits. Each chip select is limited to 256 Mbytes.

Memory Space

The MASK field can alias a memory location in different areas. The memory space associated with an individual chip select does not have to be continuous. Using the MASK field, you can set gaps in a single chip select range, essentially assigning the same chip select to different portions of the memory map.

Example

A 16 Mbyte device can be addressed in four different 64 Mbyte address locations by using a MASK value of ’hF3000. The peripheral is addressable at these address locations:

BASE + ’h00000000

BASE + ’h04000000

BASE + ’h08000000

BASE + ‘h0C000000

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Digi NS7520 manual Memory Space

Contents

NS7520 Hardware Reference Page Part number/version 90000353D Release date March Page Contents A p t e r 4 B B u s M o d u l e A p t e r 7 M e m o r y C o n t r o l l e r M o d u l e A p t e r A p t e r 1 0 S e r i a l C o n t r o l l e r M o d u l e D e Who should read this guide About this guideConventions used in this guide What’s in this guideTo read about See For Contact information Documentation updatesRelated documentation Customer supportPage About the NS7520 Key features and operating modes of the major NS7520 modules NS7520 FeaturesO u t t h e N S 7 5 2 7 5 2 0 F e a t u r e s NS7520 overview NS7520 module block diagramOperating frequency Pinout and Packaging Symbol Min Nom Max NS7520 packaging dimensionsPackaging NS7520 pinout and dimensions NS7520 BGA layout Column Description Pinout detail tables and signal descriptionsExternal bus Symbol Pin DescriptionSystem bus interface System bus interface pinoutADDR4 ADDR7ADDR6 ADDR5Do not USE System bus interface signal description Signal descriptionsMnemonic Signal Description Chip select controller pinout Chip select controllerBusy Mnemonic Signal Chip select controller signal descriptionEthernet interface MAC pinout Ethernet interface MACEthernet interface MAC signal description CRS COLGeneral-purpose I/O No connect pinsNo connect pins Serial Other Pin Serial channel Signal DescriptionDSR RTS PORTC4 RXCB/RIB ResetPORTA3 Rxda DACK1 PORTA2 Dsra AmuxSerial channel Other Description Gpio signalSerial signal Other signalClock generation and reset signal description System clock and resetSystem clock pinout Bisten System mode test supportSystem mode and system reset pinout PlltstJtag test ARM debugger ARM debugger signal descriptionJtag test pinout Trst termination GND Power supplyPower supply pinout Signal Pin DescriptionWorking with the CPU CPU performance ARM Thumb conceptARM ARM modeWorking with ARM exceptions ARM performanceException priorities Summary of ARM exceptionsException vector table Exception vector tableVector Description Address Detail of ARM exceptions Reset exceptionUndefined exception Abort exception SWI exceptionFirq exception IRQ exceptionEntering an exception Entering and exiting an exception software actionExiting an exception Abort P Reset UndefException entry/exit summary Exception entry/exit by exception typeFirq and IRQ lines Hardware InterruptsInterrupt controller Interrupt sources W . d i g i . c o m Page BBus Module Module Master Slave BBus masters and slavesCycles and BBus arbitration BBus masters and slavesBBus address decoding Address decodingAddress range Module Page SYS Module Signal mnemonic Signal name Description Signal descriptionJtag support System clock generation NS7520 clock module ARM debugExternal oscillator vs. internal PLL circuit NS7520 clock module block diagram Using the external oscillatorExternal oscillator mode hardware configuration PLL mode hardware configuration Using the PLL circuitPLL mode hardware configuration Bits Access Mnemonic Reset Description D3109 Reserved Setting the PLL frequencyPLL Settings register Setting the PLL frequency on bootup PLL Settings register bit definitionPLL multiplier Bits Access Mnemonic Reset DescriptionMHz A87 A65 A40 ND+1 PLL Settings reg Output dividerMHz A87 A65 A40 ND+1 PLL Settings reg Pllcnt PLL Control register bit definitionSysclk frequency MHz ND+1 PLL Settings registerReset circuit sources Address bit Name Description NS7520 bootstrap initializationGEN Module Address Register Module configurationGEN module address configuration GEN module hardware initializationGeneral information GEN module registersSystem Control register Address FFB0Software watchdog timeout in seconds Bclk output disableSoftware watchdog enable Software watchdog reset/interrupt selectEnable access to internal chip registers in CPU Bus monitor enableUser mode Bus interface TEA/LAST configuration Bits Access Mnemonic ResetDescription Enable ARM CPU DMA module test modeDMA module reset CPU disableTA input synchronizer NS7520 revision ID Last reset caused by external resetSystem Status register System Status register bit definitionProduct ID defined by external resistor jumpers Last reset caused by watchdog timerLast reset caused by PLL update Last reset caused by software resetAddress FFB0 000C Software Service registerTimer Control registers Software Service register bit definitionTimer interrupt mode Timer Control registers bit definitionTimer enable Timer interrupt enableTimer clock source Timer prescalerInitial timer count Current timer count Timer Status registersTimer Status registers bit definition Timer interrupt pendingPorta data direction Porta Configuration registerPorta mode configuration Porta register bit definitionPorta data register Porta ConfigurationPorta configuration AdataIN/SER1DCD PORTA1 Gpio Gpio OUT SER1CTS DONE1OUT PORTA0 SER1SPISENABLEInputs OutputsPortc data direction Portc Configuration registerPortc mode Portc register bit definitionPortc data register Portc configurationPortc configuration CdataPORTC1 Gpio Gpio OUT LEVELIRQ1=CDIR1 PORTC0 LEVELIRQ0=CDIR0 PORTC30 InterruptsAddress FFB0 0030 / 0034 Interrupt controller registersInterrupt Enable registers bit definition D01 Page Memory Controller Module About the MEM module Pin configurationMEM module pin configuration by memory type Mode A2714 A130 CSxSdram Mode A2714 A130RAS CAS Address Mnemonic Register MEM module configurationSetting the chip select address range Memory controller register mapMemory Space Refresh count value Memory Module Configuration registerEnable Dram refresh Mmcr bit definitionRefresh cycle count Enable external address multiplexingEnable A27 output RcycAMUX2 A27 and A26 bit settingsEnable A26 output Enable A25 outputBase address Chip Select Base Address registerChip Select Base Address register bit definition BasePeripheral page size Dram configuration modeDram address multiplexer select Force Bclk at end of memory cycle External TA configurationDram internal address multiplexer mode Burst memory cycle enableEeprom Write-protect the chip selectValid bit Mask Address Chip Select Option Register aChip Select Option Register a bit definition MaskWhen DRSEL=1 and DMODE=2’b00 When DRSEL=0When DRSEL=1 and DMODE=2’b01 at full speed Port size When DRSEL=1 and DMODE=10Burst access size in beats BsizeWE Ctrl Read cycle modeWrite cycle mode OE CtrlChip Select Option Register B bit definition Chip Select Option Register BSync Static memory Sram controllerSync Write Sync Read Single cycle read/writeAsync Read Burst cyclesNS7520 Dram address multiplexing Using the internal multiplexer000 001 010 011 100 101 110 111 7 5 2 0 D R a M a d d r e s s m u l t i p l e x i n g NS7520 multiplexed address outputs Internal Dram multiplexing ModeDram Using the external multiplexer FP/EDO Dram controller Dram refreshFP Dram Write FP Dram Read Normal FP Dram bus cyclesFP Dram burst cycles FP/EDO Dram burst cyclesNS7520 Sdram interconnect X32 Sdram configurationX32 Sdram interconnect BA1 Bclk CLK VCC CKE X16 Sdram configurationBA1 BA0Udqm NS7520 signal 16M Sdram signal 64M Sdram signalX16 Sdram interconnect CAS3 RAS CAS2 CAS1 CAS0Bclk CLK VCC CKE X8 Sdram configurationsNS7520 signal 16M Sdram signal X8 Sdram interconnectSdram A10/AP support Command Command definitionsSdram command definitions Mux mode X32 X16Burst length Bsize configurationCAS latency Bcyc configuration Memory timing fields SdramAddress Field Value Sdram Mode registerSdram Mode register settings FullSdram normal read Sdram read cyclesSdram burst read Sdram normal write Sdram write cyclesSdram burst write Example Peripheral page burst sizeWait Bcyc Page DMA Module Fly-by operation transfers DMA moduleDMA fly-by transfers Memory-to-memory operationDMA buffer descriptor DMA buffer descriptor Fly-by modeBuffer descriptor bit definitions Buffer descriptor bit definitionsBit Description Buffer descriptor field definitions Buffer descriptor field definitionsField Description DMA channel assignments Channel Base address DMA channel peripheral Fly-by modeDMA channel assignments Address map DMA channel registersAddress Description Address Description DMA Control register Buffer Descriptor Pointer registerChannel abort request DMA channel enableDMA operation mode DMA Control register bit definitionMemory-to-memory mode Burst transfer enableBTE Channel request source REQDestination address increment SincSource address increment DincCurrent DMA channel state shown in binary Data operand sizeCurrent DMA channel buffer descriptor index Normal completion interrupt pending DMA Status/Interrupt Enable registerDMA Status/Interrupt Enable register bit definition Error completion interrupt pendingBuffer not ready interrupt enable Premature complete interrupt enableNormal completion interrupt enable Error completion interrupt enableEthernet transmitter considerations External peripheral DMA support Ethernet receiver considerationsSignal Description Signal descriptionExternal DMA configuration Memory-to-memory modeHardware needed for external memory-to-memory DMA transfers DMA controller resetPage Ethernet Module Fifo Ethernet front-end EFEEFE transmit processing Transmit and receive FIFOsEFE receive processing DMA Receive buffer descriptor selectionExternal CAM filtering MAC module MAC module block diagramOther modules in the diagram include EFE register map EFE configurationAddress Register Register description Mcfg MaxfSupp TestErxregetxreg Erfifohetfifoh Erxbretxbc Ethernet General Control register Egcr bit definitionsAddress FF80 Erxetx Erxdmaetxdma Erxlngetxwm Erxshtefulld ErxbadEthernet General Control register bit definition Receiver in interrupt service mode Enable transmit FifoEnable transmit DMA Do not set this bit when operating the EthernetEnable full-duplex operation Enable Transmit Data register ready interruptEnable transmit data Fifo half empty interrupt Enable transmit buffer complete interruptInsert transmit source address MAC software resetInvert the transmit clock input PSOS pNA buffer descriptorsMode field Output based on EFE CSR bit Endec mode and NS7520 pinsEndec control signal cross-reference External interface modeEthernet General Status register bit definition Ethernet General Status register Egsr bit definitionsRxfdbrxskip Rxregrtxrege Rxfifohtxfifoh Rxbrtxbc Receive buffer ready Receive Fifo data availableReceive register ready Receive Fifo half fullTransmit buffer complete Receive buffer skipTransmit register empty Transmit Fifo half emptyWriting to the Ethernet Fifo Data register Endec status signal cross-referenceEthernet Fifo Data register Address FF80 0008 / FF80 000C secondary addressReading from the Ethernet Fifo Data register Fifo data FF80 Ethernet Transmit Status registerEthernet Fifo Data register bit definition Ethernet Transmit Status register bit definitionTransmit abort late collision Packet transmitted OKBroadcast packet transmitted Multicast packet transmittedTransmit abort excessive collisions TxaedTransmit abort excessive deferral TxaecTransmit abort jumbo TxaurTransmit aborted underrun TxajTxcrc Transmit CRC errorTxdef Transmit packet deferredTxcolc Ethernet Receive Status registerTransmit collision count Receive data violation event previously seen Ethernet Receive Status register bit definitionReceive buffer size in bytes Receive carrier event previously seenReceive multicast packet Receive packet has CRC errorReceive packet has dribble bit error Receive broadcast packetReceive packet is too long Receive packet has code violationReceive packet is too short Rover MAC Configuration RegisterReceive overflow MAC Configuration Register 1 bit definition RX flow control Receive enablePass ALL receive frames MAC Configuration Register 2 bit definition CRC enable Auto detect pad enableVlan pad enable PAD/CRC enablePAD operation Pad operation tableBack-to-Back Inter-Packet-Gap register bit definition Back-to-Back Inter-Packet-Gap registerBack-to-back inter-packet-gap Non back-to-back inter-packet-gap part Non-Back-to-Back Inter-Packet-Gap registerAddress FF80 040C Non-Back-to-Back Inter-Packet-Gap register bit definitionRetransmission maximum Collision Window/Collision Retry registerCollision Window/Collision Retry register bit definition Collision windowMaximum Frame register bit definition Maximum Frame registerMaximum frame length PHY Support register bit assignment PHY Support registerAddress FF80 041C Enable Jabber protectionBit mode Test registerTest pause Test backpressureShortcut pause quanta Clock select MII Management Configuration registerMII Management Configuration register bit definition Reset MII managementClks field Sysclk ratio MHz example Clks field settingsScani Scan increment single scan for read dataSingle scan for read data MII Management Command registerMII Management Command register bit definition Automatically scan for read dataMII PHY register address MII Management Address registerMII Management Address register bit definition MII PHY device addressMII write data MII Management Write Data registerAddress FF80 042C MII Management Write Data register bit definitionMII Management Read Data register bit definition MII Management Read Data registerMII read data Automatically scan for read data in progress MII Management Indicators registerMII Management Indicators register bit definition Read data not validStation Address registers Smii Status registerSmii Status register bit definition Station address octet Station Address RegisterStation Address Register 1 bit definition Station Address Register 2 bit definitionOCTET5 Station Address Register 3 bit definitionOCTET3 OCTET4Address FF80 05C0 Station Address Filter registerStation Address Filter register bit definition Address FF80 05D4 Register hash tableMulticast hash table entries and bit definitions Address FF80 05D0HT3 bit definition Address FF80 05D8Address FF80 05DC HT2 bit definitionCalculating hash table entries W . d i g i . c o m Page W . d i g i . c o m Page Serial Controller Module RTS, CTS, DTR, DSR, DCD, RI Supported featuresBit-rate generator Serial port block diagramSerial protocols Uart modeSPI mode Terminology What’s being written Value Fifo managementTransmit Fifo interface Operating in Endian modesReceive Fifo interface Processor interrupts vs. DMAUsing DMA Using processor interruptsSignals SPI master modeConfiguration SPI master transmitter SPI master receiver SPI slave modeSignals SPI slave receiver SPI slave transmitterSPI slave mode 0 and 1 two-byte transfer General-purpose I/O configurationsOperating Mode Serial Port Maximum Rate ConfigurationSerial port performance N f i g u r a t i o n Serial Channel Control Register a Serial Channel registersSerial Channel 1, 2 Control Register a Address FFD0 0000Number of stop bits Parity enableStick parity Even parity selectGeneral-purpose output 1/General-purpose Enable the transmitter with active CTSRemote loopback Local loopbackReceiver interrupt condition Enable receive DMA requestsData terminal ready active Request-to-send activeTransmitter interrupt condition Receiver interrupt enable bitsEnable transmit DMA requests Receiver interruptsTransmitter interrupts Transmitter interrupt enable bitsAddress FFD0 0004 Serial Channel 1, 2 Control Register BSerial Channel Control Register B bit definition Bitordr Enable receive character GAP timerSCC mode RcgtTransmit encoding Enable active RTS only while transmittingReceive data encoding Differential Manchester 111. a 1 is Address FFD0 0008 Serial Channel 1, 2 Status Register aCharacter Match3 Serial Channel Status Register a bit definitionCharacter Match1 Character Match2Cgap Buffer GAP timerCharacter GAP timer BgapCurrent data set ready state Current ring indicator stateDCD Current data carrier detect stateReceive parity error interrupt pending Receive framing error interrupt pendingReceive break interrupt pending Rrdy Receive overrun interrupt pendingReceive register ready interrupt pending Receive buffer closed interrupt pending Receive Fifo half-full interrupt pendingReceive Fifo full Change in CTS interrupt pending Change in DCD interrupt pendingChange in RI interrupt pending Change in DSR interrupt pendingTransmit Fifo half-empty interrupt pending Transmit register empty interrupt pendingTransmit buffer closed interrupt pending Address FFD0 000C / 4C Serial Channel 1, 2 Bit-Rate registersTempty Receive clock source Bit-rate generator enableTiming mode Serial Channel Bit-Rate register bit definitionDrive receive clock external Transmit clock sourceDrive transmit clock external BRG input clock ClkmuxTransmit clock invert Receive clock invert Tdcr If Dpll is not used and you are not usingIf Dpll is not used but you are using When Dpll is used in the application,Receive divide clock rate RdcrReceiver internal clock source TicsTransmit internal clock source RicsMax baudrates with different clock sources With the 18.432MHz crystal using Xtale as the clock sourceNreg 16X @ 55.296MHz With the 18.432MHz crystal using Sysclk as the clock sourceBit rate examples X1 mode X8 mode X16 modeSerial Channel 1, 2 Fifo registers Address FFD0 0010Data Serial Channel 1, 2 Receive Buffer Gap TimerAddress FFD0 0014 DataAddress FFD0 0018 Serial Channel 1, 2 Receive Character Gap TimerRegister diagram and bit assignment Serial Channel Receive Buffer Gap Timer bit definitionCT value Serial Channel Receive Character Gap Timer bit definitionAddress FFD0 0020 Serial Channel 1,2 Receive Match registerSerial Channel 1, 2 Receive Match Mask register Address FFD0 001C / 5CRMMB3 Serial Channel Receive Match Mask register bit definitionRMMB1 RMMB2Page Electrical Characteristics Sym Parameter Conditions Min Typ Max Unit DC characteristicsRecommended operating conditions Recommended operating thermal conditionsDC characteristics outputs Input/Output characteristicsPad pullup and pulldown characteristics DC characteristics inputsInternal pullup characteristics Maximum voltage ratings AC characteristicsAC electrical specifications Absolute maximum ratingsMDC, MDIO, TXEN, TXER, TXD30 Estimated Signal Load pF Device loadsSystem loading details PORTA3, PORTA1, PORTC3, PORTC1MDC, TXD30, TXER, TXEN, TDO Oscillator CharacteristicsSignal Derating ns/pF Output buffer derating by load capacitanceNS7520 TimingSpecifications Timing DiagramsReset timing parameters ResettimingNum Description Min Typ Max Units Sram timing parameters Sram timingNum Description Min Max Unit CS* controlled read wait = Sram readSram burst read CS* controlled read wait = 0, Bcyc = CS controlled write internal and external, wait = Sram writeSram burst write OE* controlled read wait = Sram OE readSram OE burst read WE* controlled write wait = Sram WE writeSram WE burst write Sdram timing parameters Sdram timingSdram read, CAS latency = Sdram readActive Read Inhibit Prechg Bterm Sdram burst read Sdram burst read Sdram write Sdram writeSdram burst write Sdram burst writeSdram refresh Sdram load modeFP Dram timing parameters FP Dram timingFast Page read FP Dram readFast Page burst read FP Dram burst readFast Page write FP Dram writeFast Page burst write FP Dram burst writeFast page refresh Rcyc = FprefreshcyclesCAS3 CAS2 CAS1 CAS0 RF1 RF2 RF3 RF4 RF5 RF8 Ethernet timing parameters Ethernet timingEthernet cam timing Ethernet PHY timingNum Description Min Max Units Jtag arm ice timing diagramJtag timing Jtag arm ice timing parametersJtag bscan timing parameters Jtag bscan timing diagramExternal DMA timing parameters External DMA timingFly-by external DMA Memory-to-memory external DMA 2T SYS Serial internal timing characteristicsSerial external timing characteristics Serial internal/external timingSynchronous serial external clock Synchronous serial internal clockGpio timing Gpio timing diagramGpio timing parameters Page Index CPU Non-Back-to-BackInter-Packet-Gap register FP Dram Portc NET+ARM PORTC0 Receiver interrupts 229 transmitter interrupts Undefined exception 32 Page