Digi NS7520 manual BBus masters and slaves, Cycles and BBus arbitration, Module Master Slave

B B u s m a s t e r s a n d s l a v e s

BBus masters and slaves

The BBus module consists of bus master and bus slave modules. The BBus state machine allows each bus master to control the bus in a round-robin manner. If a bus master does not require the bus resources when its turn comes around, that bus is skipped until the next round-robin slot. Each potential bus master presents the BBus with request and attribute signals. Once mastership is granted, the targeted device is selected.

Table 19 illustrates bus master and slave modules.

Module	Master	Slave
CPU module	Y	Y
BUS module	Y	Y
EFE module		Y
DMA module	Y	Y
GEN module		Y
MEM module		Y
SER module		Y

Table 19: BBus masters and slaves

Cycles and BBus arbitration

During a normal cycle, each bus master cycle is allowed only one read/write cycle if another bus master is waiting. There are two exceptions to this rule: burst transactions and read-modify-write transactions.

In a burst transaction, the master can perform more than one read or write cycle. In a read-modify-write transaction, the bus master performs one read and write cycle to the same location.

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