Digi NS7520 manual Bits Access Mnemonic Reset Description, Output divider, PLL multiplier

					S Y S M o d u l e
Bits	Access	Mnemonic	Reset	Description
D08:07	Read	IS	‘b10	Charge pump current
	only			Sets the PLL’s charge pump current.
				The IS field defaults to binary ‘b10 when address
				lines [8:7] are not pulled down on powerup. The
				IS value is based on the value in the ND field.
				(ND+1)	IS
				1–3	‘b00
				4–7	‘b01
				8–15	‘b10
				16–32	‘b11
D06:05	Read	FS	‘b00	Output divider
	only			Sets the PLL’s output divider.
				The FS field defaults to ‘b00 when address lines
				[6:5] are not pulled down on powerup. This is the
				correct setting for all frequencies and should
				never be adjusted.
D04:00	Read	ND	‘b01011	PLL multiplier
	only			Sets the PLL’s multiplier, which determines BCLK
				frequency.

BCLK frequency is based on tis formula: BCLK = (crystal/4) (ND+1)

The ND field defaults to ‘b01011 to produce 55MHz (with a 18.432MHz crystal) when address lines A[4:0] are not pulled down on powerup.

Table 21: PLL Settings register bit definition

The next table shows the 32 frequencies that can be produced with an 18.432MHz crystal. A 0 on an address indicates that a 2.7K pulldown resistor must be connected to that address line. The table shows the IS, FS, and ND fields, and the resulting value in the PLL Settings register.

MHz	A[8:7]	IS	A[6:5]	FS	A[4:0]	ND+1	PLL Settings reg	Notes
4.6	01	00	11	00	10100	00001	0x00000000
9.2	01	00	11	00	10101	00010	0x00000001
13.8	01	00	11	00	10110	00011	0x00000002

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