M e m o r y C o n t r o l l e r M o d u l e

Chip Select Option Register A

Address: FFC0 0014/24/34/44/54

The Chip Select Option Register A defines the physical size of the chip select, as well as other features. Each chip select can be configured in size from 4 Kbytes to

4 Gbytes.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MASK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MASK

 

 

WAIT[3:0]

 

BCYC[1:0]

 

BSIZE

 

PS

OE

WE

 

 

 

 

 

 

CTRL_

CTRL_

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

D31:12

R/W

MASK

0

Mask Address

 

 

 

 

Controls the size of the memory peripheral

 

 

 

 

decode space. Can also be used to “alias”

 

 

 

 

the peripheral device in different areas of

 

 

 

 

the memory map.

 

 

 

 

See "Setting the chip select address range"

 

 

 

 

on page 88 for more information.

 

 

 

 

 

D11:08

R/W

WAIT[3:0]

0 for

Memory timing control fields

 

 

 

CS[4:1],

The WAIT field controls the number of wait

 

 

 

‘b1111

states for all single cycle memory transfers

 

 

 

for CS0

and the first memory cycle of a burst

 

 

 

 

transaction. The complete WAIT field is the

D07:06

R/W

BCYC[1:0]

0

concatenation of the four WAIT bits in this

 

 

 

 

register and the two WAIT bits in Chip Select Option

Register B.

The BCYC field controls the number of clock cycles for the secondary portion of a burst cycle. The complete BCYC field is the concatenation of the two BCYC bits in this register and the two BCYC bits in the Chip Select Option Register B.

Table 38: Chip Select Option Register A bit definition

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Digi NS7520 manual Chip Select Option Register a bit definition, Mask Address, Memory timing control fields