Digi NS7520 manual Using processor interrupts, Using DMA

S P I m o d e

Using processor interrupts

When using processor interrupts, the processor can read one long word (4 bytes) of data from the receive FIFO when the RRDY bit in Serial Channel Status Register A is active high. This long word can have 1, 2, 3, or 4 bytes of valid data within the word. The number of valid bytes is determined by the bit encoding in the RXFDB field in Serial Channel Status Register A. The RXFDB field must be read before the FIFO Data register is read.

The RBC (receive buffer closed) bit in Serial Channel Status register A indicates that a receive data buffer has been closed and receiver status can be read from that register. Before additional data can be read from the FIFO, the RBC bit must be acknowledged by writing a 1 to the same bit position in the Serial Channel Status Register A.

This is the recommended process flow for the serial port receiver interrupt service routine:

1Read Serial Channel Status Register A.

2If RBC is true:

a Record receiver buffer closed status (if desired).

b Write a 1 to the RBC bit position in Serial Channel Status Register A. c Read Serial Channel Status Register A again.

3If RRDY is true:

a Read the data FIFO.

b Use the RXFDB field to pick valid bytes.

To facilitate an interrupt when either the RRDY or RBC status bits are active, the processor must set one or both of the corresponding interrupt enables — ERXDRDY, ERXBC — in Serial Channel Control Register A. The appropriate interrupt enable bit — SER 1 RX, SER 2 RX — in the GEN module Interrupt Enable register must also be set.

Using DMA

When using the DMA controller, the processor must interface with the DMA channel registers and the DMA buffer descriptor block attached to DMA channels 7 and 9. To facilitate the use of receive DMA, the ERXDMA bit in Serial Channel Control Register A must be set active high and the serial receiver interrupts should be disabled.

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