Digi NS7520 manual Ethernet Receive Status register bit definition, Receive buffer size in bytes

E t h e r n e t M o d u l e

Register bit assignment

Bits	Access	Mnemonic	Reset	Description
D31:16	R	RXSIZE	0	Receive buffer size in bytes
				Provides the number of bytes contained in the next
				packet to be read from the Ethernet receive FIFO.
				When using DMA mode, the RXSIZE field is also
				copied to the buffer length field in the DMA buffer
				descriptor.
D15	R	RXCE	0	Receive carrier event previously seen
				Set to 1 to indicate that the MAC received a carrier
				event from the Ethernet PHY since the last time a
				receive packet event was recorded in this status
				register. The carrier event is not associated with
				this particular packet.
				A carrier event is defined as any activity on the
				receive channel that does not result in a packet
				receive attempt.
D14	R	RXDV	0	Receive data violation event previously seen
				Set to 1 to indicate that, at some point since the
				last recorded receive packet, a receive data
				violation was detected, noted, and reported with
				this receive packet event. The receive data event is
				not associated with this particular packet.
				A receive data violation event occurs when there is
				no valid preamble and start frame delimiter (SFD) in
				the data stream.
D13	R	RXOK	0	Receive packet OK
				Set to 1 to indicate that the next packet in the
				receive FIFO has been received without any errors.

When this bit is set, the RXREGR and RXFIFOH bits in the Ethernet General Status register become active and the packet can be emptied (using interrupts, polling, or DMA). When the packet has been emptied, RXREGR and RXFIFOH become inactive until the next receive buffer is ready.

Table 59: Ethernet Receive Status register bit definition

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