S e r i a l C o n t r o l l e r M o d u l e

Serial Channel 1, 2 Control Register B

Address: FFD0 0004 / 44

31

30

29

 

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RDM1

RDM2

RDM3

 

RDM4

RBGT

RCGT

 

Reserved

 

MODE

BIT

 

Reserved

 

 

 

 

ORDR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

 

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RTS

 

Reserved

 

 

TENC

 

 

RDEC

 

 

 

Reserved

 

 

TX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register bit assignment

Bit

Access

Mnemonic

Reset

Description

 

 

 

 

 

D31

R/W

RDM1

0

Enable receive data match 1/2/3/4

D30

R/W

RDM2

0

When the serial channel is configured to

D29

R/W

RDM3

0

operate in UART mode, the RDM bits enable

D28

R/W

RDM4

0

the receive data match comparators. A receive

data match comparison detection can be used

 

 

 

 

 

 

 

 

to close the current receive buffer descriptor.

 

 

 

 

The last byte in the current receive data buffer

 

 

 

 

contains the match character. Each of these

 

 

 

 

bits enables the respective byte in the Receive

 

 

 

 

Match register.

 

 

 

 

 

D27

R/W

RBGT

0

Enable receive buffer GAP timer

 

 

 

 

Detects the maximum allowed time from when

 

 

 

 

the first byte is placed into the receive data

 

 

 

 

buffer and when the receive data buffer is

 

 

 

 

closed.

When RBGT is set to 1, the BGAP field in Serial Channel Status Register A is set when the timeout value defined in the Receive Buffer GAP Timer register has expired.

Table 88: Serial Channel Control Register B bit definition

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Digi NS7520 Serial Channel 1, 2 Control Register B, Address FFD0 0004, Serial Channel Control Register B bit definition