S t a t i c m e m o r y ( S R A M ) c o n t r o l l e r

T1

TW

T2

T1

TW TW T2

T1

TW

T2

BCLK

 

 

 

 

 

 

 

ADDR

 

 

 

 

 

 

 

BEn_

 

 

 

 

 

 

 

CS0_

 

 

 

 

 

 

 

CS1_

 

 

 

 

 

 

 

R/W_

 

 

 

 

 

 

 

WE_

 

 

 

 

 

 

 

OE_

 

 

 

 

 

 

 

DATA

 

*

 

*

 

 

*

TA_

 

 

 

 

 

 

 

 

 

 

 

 

Async Write

 

Async Read

 

Async Write

Figure 7: Asynchronous SRAM cycles

The BE_, OE_, and WE_ signals transition based on the falling edge of BCLK.

The BE_, OE_, or WE_ signal transitions low on the first falling edge after CS[4:0]_ is asserted.

The BE_, OE_, or WE_ signal transitions high on the first falling edge after TA_ is recognized (TA_ is sampled using the rising edge of BCLK).

The rising edge of BCLK where TA_ is low defines the last TW cycle. Read data is sampled and write data is valid on the rising edge of BCLK where TA_ is low.

Burst cycles

The SRAM controller supports both read and write burst cycles. Figure 8 shows a synchronous SRAM burst read cycle.

1 0 4

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

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Image 118
Digi NS7520 manual Burst cycles, Async Read