Digi NS7520 manual Dram refresh, FP/EDO Dram controller

M e m o r y C o n t r o l l e r M o d u l e

Setting the DMUXS bit indicates that the internal address multiplexer must be disabled when the specific chip select is activated. The NS7520 drives the address bus using standard addressing without any multiplexing, but only for the specific chip select, the internal address multiplexer is disabled, and the multiplexer indicator is driven out the PORTA2 pin.

The PORTA2 signal is driven active high during the CAS addressing portion for FP and EDO DRAM, as well as during the SDRAM write command, read command, and load mode command. The NS7520 drives the SDRAM load mode command on its lower address pins. At all other times, the PORTA2 signal is driven active low.

DRAM refresh

The NS7520 MEM module executes a refresh cycle that supports Fast Page (FP), EDO and SDRAM devices. The FP and EDO devices are refreshed using the CAS-before-RAS technique; SDRAM devices re refreshed using the REFRESH command.

"fp_refresh_cycles" on page 294 provides a timing diagram of DRAM refresh cycles based in the RCYC setting. This diagram illustrates the CAS-before-RAS refresh cycles for FP and EDO DRAM. The RCYC field controls the timing of CAS and RAS in the refresh cycle.

FP/EDO DRAM controller

The memory controller module contains an integrated FP/EDO DRAM controller. Each chip select can be configured to operate using DRAM. The DRAM controller supports these features:

FP (Fast Page) mode, EDO DRAMs, and SDRAM (see "SDRAM," beginning on page 111).

CAS before RAS refresh operation Programmable refresh timer

Background refresh cycles (refresh while another non-DRAM chip select access is in progress)

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