E l e c t r i c a l C h a r a c t e r i s t i c s

SDRAM timing

BCLK max frequency: 55.296 MHz

Operating conditions:

Temperature:

-15.00 (min)

110.00 (max)

Voltage:

1.60 (min)

1.40 (max)

Output load:

25.0pf

 

Input drive:

CMOS buffer

 

SDRAM timing parameters

Num

Description

Min

Max

Unit

 

 

 

 

 

36

BCLK high to BE*/DQM* valid

 

15.5

ns

 

 

 

 

 

6

BCLK high to non-muxed address valid

5

13.5

ns

 

 

 

 

 

9

BCLK high to data out valid

 

14

ns

 

 

 

 

 

13

BCLK high to data out high impedance

 

13

ns

 

 

 

 

 

10

Data in valid to BCLK high (setup)

5

 

ns

 

 

 

 

 

11

BCLK high to data in invalid (hold)

3

 

ns

 

 

 

 

 

27

BCLK high to CS* valid

 

15.5

ns

 

 

 

 

 

30

BCLK high to TA* valid

 

13.5

ns

 

 

 

 

 

31

BCLK high to TEA* valid

 

16

ns

 

 

 

 

 

37

BCLK high to PORTA2/AMUX valid

 

14

ns

 

 

 

 

 

35

BCLK high to muxed address valid

6

14.5

ns

 

 

 

 

 

34

BCLK high to CAS* valid

 

12

ns

 

 

 

 

 

12

BCLK high to RW* valid

 

13.5

ns

 

 

 

 

 

w w w . d i g i . c o m

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Page 295
Image 295
Digi NS7520 manual Sdram timing parameters