Digi NS7520 manual MAC Configuration Register, Rover, Receive overflow

E F E c o n f i g u r a t i o n

Bits	Access	Mnemonic	Reset	Description
D05	R	ROVER	0	Receive overflow
				Set to 1 to indicate that a receive FIFO overrun
				condition has occurred.
				An overrun condition occurs when the FIFO
				becomes full while receiving an Ethernet packet.
				This condition indicates that the DMA controller
				was not able to empty the FIFO at a fast enough
				rate compared to the rate that information was
				received from the Ethernet medium for one of
				these reasons:
				The DMA controller was not configured for
				bursting.
				The memory peripheral device was not
				configured for bursting.
				The memory peripheral device is too slow to
				support the Ethernet interface.
				When this bit is set, the RXREGR and RXFIFOH bits
				in the Ethernet General Status register remain
				inactive. The bad receive packet is flushed
				immediately from the FIFO.
D04:00	N/A	Reserved	N/A	N/A

Table 59: Ethernet Receive Status register bit definition

MAC Configuration Register 1

Address: FF80 0400

MAC Configuration Register 1 contains bits that control functionality within the Ethernet MAC block.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							Reserved
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SRST	SIM	Reserved		RPEM	RPER	RPEM	RPET		Reserved		LOOP	TX	RX	PALL	RXEN
	RST			CSR	FUN	CST	FUN				BK	FLOW	FLOW	RX

1 7 8 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6