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Digi NS7520 manual Entering and exiting an exception software action, Entering an exception

Models: NS7520

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W o r k i n g w i t h t h e C P U

Entering and exiting an exception (software action)

The ARM7TDMI performs specific steps when handling exceptions.

Entering an exception

When handling an exception, ARM7TDMI does this:

1Preserves the address of the next instruction in the appropriate Link register.

–If the exception has been entered from the ARM state, the address of the next instruction is copied into the Link register. The address is either current PC + 4 or PC + 8, depending on the exception. (See Table 18: "Exception entry/exit by exception type" on page 38.)

–If the exception has been entered from Thumb state, the value written into the Link register is the current PC offset by a value that lets the program continue from the correct place on return from the exception.

The exception handler does not need to determine from which state the exception was entered. With an SWI, for example, MOVS PC, R14_SVC always returns to the next instruction whether executed in ARM or Thumb state.

2Copies the CPSR into the appropriate SPSR.

3Forces the CPSR mode bits to a value that depends on the exception.

4Forces the PC to fetch the next instruction from the relevant exception vector.

5Sets the I (for IRQ interrupts) or F (for FIRQ interrupts) bits to disable interrupts to prevent unmanageable nesting of exceptions.

Note: If the processor is in Thumb state when an exception occurs, it automatically switches into ARM state when the PC is loaded with the exception vector address.

Exiting an exception

On completion, ARM7TDMI does this:

1Moves the Link register, minus the offset where appropriate, to the PC. The offset value varies depending on the type of exception.

2Copies the SPSR back to the CPSR.

3Clears the interrupt disable flags, if they were set on entry.

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Digi NS7520 manual Entering and exiting an exception software action, Entering an exception, Exiting an exception

Contents

NS7520 Hardware Reference Page Part number/version 90000353D Release date March Page Contents A p t e r 4 B B u s M o d u l e A p t e r 7 M e m o r y C o n t r o l l e r M o d u l e A p t e r A p t e r 1 0 S e r i a l C o n t r o l l e r M o d u l e D e Who should read this guide About this guideWhat’s in this guide Conventions used in this guideTo read about See For Contact information Documentation updatesRelated documentation Customer supportPage About the NS7520 Key features and operating modes of the major NS7520 modules NS7520 FeaturesO u t t h e N S 7 5 2 7 5 2 0 F e a t u r e s NS7520 overview NS7520 module block diagramOperating frequency Pinout and Packaging NS7520 packaging dimensions Symbol Min Nom MaxPackaging NS7520 pinout and dimensions NS7520 BGA layout Column Description Pinout detail tables and signal descriptionsExternal bus Symbol Pin DescriptionSystem bus interface System bus interface pinoutADDR4 ADDR7ADDR6 ADDR5Do not USE Signal descriptions System bus interface signal descriptionMnemonic Signal Description Chip select controller Chip select controller pinoutBusy Mnemonic Signal Chip select controller signal descriptionEthernet interface MAC pinout Ethernet interface MACEthernet interface MAC signal description CRS COLGeneral-purpose I/O No connect pinsNo connect pins Serial Other Pin Serial channel Signal DescriptionDSR RTS PORTC4 RXCB/RIB ResetPORTA3 Rxda DACK1 PORTA2 Dsra AmuxSerial channel Other Description Gpio signalSerial signal Other signalSystem clock and reset Clock generation and reset signal descriptionSystem clock pinout Bisten System mode test supportSystem mode and system reset pinout PlltstARM debugger signal description Jtag test ARM debuggerJtag test pinout Trst termination GND Power supplyPower supply pinout Signal Pin DescriptionWorking with the CPU CPU performance ARM Thumb conceptARM ARM modeWorking with ARM exceptions ARM performanceException priorities Summary of ARM exceptionsException vector table Exception vector tableVector Description Address Reset exception Detail of ARM exceptionsUndefined exception Abort exception SWI exceptionFirq exception IRQ exceptionEntering and exiting an exception software action Entering an exceptionExiting an exception Abort P Reset UndefException entry/exit summary Exception entry/exit by exception typeHardware Interrupts Firq and IRQ linesInterrupt controller Interrupt sources W . d i g i . c o m Page BBus Module Module Master Slave BBus masters and slavesCycles and BBus arbitration BBus masters and slavesAddress decoding BBus address decodingAddress range Module Page SYS Module Signal description Signal mnemonic Signal name DescriptionJtag support ARM debug System clock generation NS7520 clock moduleExternal oscillator vs. internal PLL circuit NS7520 clock module block diagram Using the external oscillatorExternal oscillator mode hardware configuration PLL mode hardware configuration Using the PLL circuitPLL mode hardware configuration Bits Access Mnemonic Reset Description D3109 Reserved Setting the PLL frequencyPLL Settings register Setting the PLL frequency on bootup PLL Settings register bit definitionPLL multiplier Bits Access Mnemonic Reset DescriptionMHz A87 A65 A40 ND+1 PLL Settings reg Output dividerMHz A87 A65 A40 ND+1 PLL Settings reg PLL Control register bit definition PllcntSysclk frequency MHz ND+1 PLL Settings registerReset circuit sources Address bit Name Description NS7520 bootstrap initializationGEN Module Address Register Module configurationGEN module address configuration GEN module hardware initializationGeneral information GEN module registersSystem Control register Address FFB0Software watchdog timeout in seconds Bclk output disableSoftware watchdog enable Software watchdog reset/interrupt selectBus monitor enable Enable access to internal chip registers in CPUUser mode Bus interface TEA/LAST configuration Bits Access Mnemonic ResetDescription Enable ARM CPU DMA module test modeCPU disable DMA module resetTA input synchronizer NS7520 revision ID Last reset caused by external resetSystem Status register System Status register bit definitionProduct ID defined by external resistor jumpers Last reset caused by watchdog timerLast reset caused by PLL update Last reset caused by software resetAddress FFB0 000C Software Service registerTimer Control registers Software Service register bit definitionTimer interrupt mode Timer Control registers bit definitionTimer enable Timer interrupt enableTimer prescaler Timer clock sourceInitial timer count Current timer count Timer Status registersTimer Status registers bit definition Timer interrupt pendingPorta data direction Porta Configuration registerPorta mode configuration Porta register bit definitionPorta data register Porta ConfigurationPorta configuration AdataIN/SER1DCD PORTA1 Gpio Gpio OUT SER1CTS DONE1OUT PORTA0 SER1SPISENABLEInputs OutputsPortc data direction Portc Configuration registerPortc mode Portc register bit definitionPortc data register Portc configurationPortc configuration CdataPORTC1 Gpio Gpio OUT LEVELIRQ1=CDIR1 PORTC0 LEVELIRQ0=CDIR0 PORTC30 InterruptsAddress FFB0 0030 / 0034 Interrupt controller registersInterrupt Enable registers bit definition D01 Page Memory Controller Module About the MEM module Pin configurationMEM module pin configuration by memory type Mode A2714 A130 CSxMode A2714 A130 SdramRAS CAS Address Mnemonic Register MEM module configurationSetting the chip select address range Memory controller register mapMemory Space Refresh count value Memory Module Configuration registerEnable Dram refresh Mmcr bit definitionRefresh cycle count Enable external address multiplexingEnable A27 output RcycAMUX2 A27 and A26 bit settingsEnable A26 output Enable A25 outputBase address Chip Select Base Address registerChip Select Base Address register bit definition BaseDram configuration mode Peripheral page sizeDram address multiplexer select Force Bclk at end of memory cycle External TA configurationDram internal address multiplexer mode Burst memory cycle enableWrite-protect the chip select EepromValid bit Mask Address Chip Select Option Register aChip Select Option Register a bit definition MaskWhen DRSEL=0 When DRSEL=1 and DMODE=2’b00When DRSEL=1 and DMODE=2’b01 at full speed Port size When DRSEL=1 and DMODE=10Burst access size in beats BsizeWE Ctrl Read cycle modeWrite cycle mode OE CtrlChip Select Option Register B bit definition Chip Select Option Register BSync Static memory Sram controllerSync Write Sync Read Single cycle read/writeAsync Read Burst cyclesUsing the internal multiplexer NS7520 Dram address multiplexing000 001 010 011 100 101 110 111 7 5 2 0 D R a M a d d r e s s m u l t i p l e x i n g Internal Dram multiplexing Mode NS7520 multiplexed address outputsDram Using the external multiplexer FP/EDO Dram controller Dram refreshFP Dram Write FP Dram Read Normal FP Dram bus cyclesFP Dram burst cycles FP/EDO Dram burst cyclesX32 Sdram configuration NS7520 Sdram interconnectX32 Sdram interconnect BA1 Bclk CLK VCC CKE X16 Sdram configurationBA1 BA0Udqm NS7520 signal 16M Sdram signal 64M Sdram signalX16 Sdram interconnect CAS3 RAS CAS2 CAS1 CAS0Bclk CLK VCC CKE X8 Sdram configurationsNS7520 signal 16M Sdram signal X8 Sdram interconnectSdram A10/AP support Command Command definitionsSdram command definitions Mux mode X32 X16Burst length Bsize configurationCAS latency Bcyc configuration Memory timing fields SdramAddress Field Value Sdram Mode registerSdram Mode register settings FullSdram normal read Sdram read cyclesSdram burst read Sdram normal write Sdram write cyclesSdram burst write Example Peripheral page burst sizeWait Bcyc Page DMA Module Fly-by operation transfers DMA moduleDMA fly-by transfers Memory-to-memory operationDMA buffer descriptor DMA buffer descriptor Fly-by modeBuffer descriptor bit definitions Buffer descriptor bit definitionsBit Description Buffer descriptor field definitions Buffer descriptor field definitionsField Description Channel Base address DMA channel peripheral Fly-by mode DMA channel assignmentsDMA channel assignments DMA channel registers Address mapAddress Description Address Description DMA Control register Buffer Descriptor Pointer registerChannel abort request DMA channel enableDMA operation mode DMA Control register bit definitionBurst transfer enable Memory-to-memory modeBTE Channel request source REQDestination address increment SincSource address increment DincData operand size Current DMA channel state shown in binaryCurrent DMA channel buffer descriptor index Normal completion interrupt pending DMA Status/Interrupt Enable registerDMA Status/Interrupt Enable register bit definition Error completion interrupt pendingBuffer not ready interrupt enable Premature complete interrupt enableNormal completion interrupt enable Error completion interrupt enableEthernet transmitter considerations External peripheral DMA support Ethernet receiver considerationsSignal Description Signal descriptionExternal DMA configuration Memory-to-memory modeHardware needed for external memory-to-memory DMA transfers DMA controller resetPage Ethernet Module Fifo Ethernet front-end EFETransmit and receive FIFOs EFE transmit processingEFE receive processing DMA Receive buffer descriptor selectionExternal CAM filtering MAC module MAC module block diagramOther modules in the diagram include EFE configuration EFE register mapAddress Register Register description Mcfg MaxfSupp TestErxregetxreg Erfifohetfifoh Erxbretxbc Ethernet General Control register Egcr bit definitionsAddress FF80 Erxetx Erxdmaetxdma Erxlngetxwm Erxshtefulld ErxbadEthernet General Control register bit definition Receiver in interrupt service mode Enable transmit FifoEnable transmit DMA Do not set this bit when operating the EthernetEnable full-duplex operation Enable Transmit Data register ready interruptEnable transmit data Fifo half empty interrupt Enable transmit buffer complete interruptInsert transmit source address MAC software resetInvert the transmit clock input PSOS pNA buffer descriptorsMode field Output based on EFE CSR bit Endec mode and NS7520 pinsEndec control signal cross-reference External interface modeEthernet General Status register Egsr bit definitions Ethernet General Status register bit definitionRxfdbrxskip Rxregrtxrege Rxfifohtxfifoh Rxbrtxbc Receive buffer ready Receive Fifo data availableReceive register ready Receive Fifo half fullTransmit buffer complete Receive buffer skipTransmit register empty Transmit Fifo half emptyWriting to the Ethernet Fifo Data register Endec status signal cross-referenceEthernet Fifo Data register Address FF80 0008 / FF80 000C secondary addressReading from the Ethernet Fifo Data register Fifo data FF80 Ethernet Transmit Status registerEthernet Fifo Data register bit definition Ethernet Transmit Status register bit definitionTransmit abort late collision Packet transmitted OKBroadcast packet transmitted Multicast packet transmittedTransmit abort excessive collisions TxaedTransmit abort excessive deferral TxaecTransmit abort jumbo TxaurTransmit aborted underrun TxajTxcrc Transmit CRC errorTxdef Transmit packet deferredEthernet Receive Status register TxcolcTransmit collision count Receive data violation event previously seen Ethernet Receive Status register bit definitionReceive buffer size in bytes Receive carrier event previously seenReceive multicast packet Receive packet has CRC errorReceive packet has dribble bit error Receive broadcast packetReceive packet has code violation Receive packet is too longReceive packet is too short MAC Configuration Register RoverReceive overflow MAC Configuration Register 1 bit definition Receive enable RX flow controlPass ALL receive frames MAC Configuration Register 2 bit definition CRC enable Auto detect pad enableVlan pad enable PAD/CRC enablePAD operation Pad operation tableBack-to-Back Inter-Packet-Gap register Back-to-Back Inter-Packet-Gap register bit definitionBack-to-back inter-packet-gap Non back-to-back inter-packet-gap part Non-Back-to-Back Inter-Packet-Gap registerAddress FF80 040C Non-Back-to-Back Inter-Packet-Gap register bit definitionRetransmission maximum Collision Window/Collision Retry registerCollision Window/Collision Retry register bit definition Collision windowMaximum Frame register Maximum Frame register bit definitionMaximum frame length PHY Support register bit assignment PHY Support registerAddress FF80 041C Enable Jabber protectionBit mode Test registerTest backpressure Test pauseShortcut pause quanta Clock select MII Management Configuration registerMII Management Configuration register bit definition Reset MII managementClks field Sysclk ratio MHz example Clks field settingsScani Scan increment single scan for read dataSingle scan for read data MII Management Command registerMII Management Command register bit definition Automatically scan for read dataMII PHY register address MII Management Address registerMII Management Address register bit definition MII PHY device addressMII write data MII Management Write Data registerAddress FF80 042C MII Management Write Data register bit definitionMII Management Read Data register MII Management Read Data register bit definitionMII read data Automatically scan for read data in progress MII Management Indicators registerMII Management Indicators register bit definition Read data not validSmii Status register Station Address registersSmii Status register bit definition Station address octet Station Address RegisterStation Address Register 1 bit definition Station Address Register 2 bit definitionOCTET5 Station Address Register 3 bit definitionOCTET3 OCTET4Station Address Filter register Address FF80 05C0Station Address Filter register bit definition Address FF80 05D4 Register hash tableMulticast hash table entries and bit definitions Address FF80 05D0HT3 bit definition Address FF80 05D8Address FF80 05DC HT2 bit definitionCalculating hash table entries W . d i g i . c o m Page W . d i g i . c o m Page Serial Controller Module RTS, CTS, DTR, DSR, DCD, RI Supported featuresBit-rate generator Serial port block diagramSerial protocols Uart modeSPI mode Terminology What’s being written Value Fifo managementTransmit Fifo interface Operating in Endian modesReceive Fifo interface Processor interrupts vs. DMAUsing DMA Using processor interruptsSPI master mode SignalsConfiguration SPI master transmitter SPI master receiver SPI slave modeSignals SPI slave receiver SPI slave transmitterSPI slave mode 0 and 1 two-byte transfer General-purpose I/O configurationsConfiguration Operating Mode Serial Port Maximum RateSerial port performance N f i g u r a t i o n Serial Channel Control Register a Serial Channel registersSerial Channel 1, 2 Control Register a Address FFD0 0000Number of stop bits Parity enableStick parity Even parity selectGeneral-purpose output 1/General-purpose Enable the transmitter with active CTSRemote loopback Local loopbackReceiver interrupt condition Enable receive DMA requestsData terminal ready active Request-to-send activeTransmitter interrupt condition Receiver interrupt enable bitsEnable transmit DMA requests Receiver interruptsTransmitter interrupts Transmitter interrupt enable bitsSerial Channel 1, 2 Control Register B Address FFD0 0004Serial Channel Control Register B bit definition Bitordr Enable receive character GAP timerSCC mode RcgtEnable active RTS only while transmitting Transmit encodingReceive data encoding Differential Manchester 111. a 1 is Address FFD0 0008 Serial Channel 1, 2 Status Register aCharacter Match3 Serial Channel Status Register a bit definitionCharacter Match1 Character Match2Cgap Buffer GAP timerCharacter GAP timer BgapCurrent data set ready state Current ring indicator stateDCD Current data carrier detect stateReceive framing error interrupt pending Receive parity error interrupt pendingReceive break interrupt pending Receive overrun interrupt pending RrdyReceive register ready interrupt pending Receive Fifo half-full interrupt pending Receive buffer closed interrupt pendingReceive Fifo full Change in CTS interrupt pending Change in DCD interrupt pendingChange in RI interrupt pending Change in DSR interrupt pendingTransmit register empty interrupt pending Transmit Fifo half-empty interrupt pendingTransmit buffer closed interrupt pending Serial Channel 1, 2 Bit-Rate registers Address FFD0 000C / 4CTempty Receive clock source Bit-rate generator enableTiming mode Serial Channel Bit-Rate register bit definitionTransmit clock source Drive receive clock externalDrive transmit clock external Clkmux BRG input clockTransmit clock invert Receive clock invert Tdcr If Dpll is not used and you are not usingIf Dpll is not used but you are using When Dpll is used in the application,Receive divide clock rate RdcrReceiver internal clock source TicsTransmit internal clock source RicsWith the 18.432MHz crystal using Xtale as the clock source Max baudrates with different clock sourcesNreg 16X @ 55.296MHz With the 18.432MHz crystal using Sysclk as the clock sourceBit rate examples X1 mode X8 mode X16 modeSerial Channel 1, 2 Fifo registers Address FFD0 0010Data Serial Channel 1, 2 Receive Buffer Gap TimerAddress FFD0 0014 DataAddress FFD0 0018 Serial Channel 1, 2 Receive Character Gap TimerRegister diagram and bit assignment Serial Channel Receive Buffer Gap Timer bit definitionCT value Serial Channel Receive Character Gap Timer bit definitionAddress FFD0 0020 Serial Channel 1,2 Receive Match registerSerial Channel 1, 2 Receive Match Mask register Address FFD0 001C / 5CRMMB3 Serial Channel Receive Match Mask register bit definitionRMMB1 RMMB2Page Electrical Characteristics Sym Parameter Conditions Min Typ Max Unit DC characteristicsRecommended operating conditions Recommended operating thermal conditionsDC characteristics outputs Input/Output characteristicsPad pullup and pulldown characteristics DC characteristics inputsInternal pullup characteristics Maximum voltage ratings AC characteristicsAC electrical specifications Absolute maximum ratingsMDC, MDIO, TXEN, TXER, TXD30 Estimated Signal Load pF Device loadsSystem loading details PORTA3, PORTA1, PORTC3, PORTC1MDC, TXD30, TXER, TXEN, TDO Oscillator CharacteristicsSignal Derating ns/pF Output buffer derating by load capacitanceNS7520 TimingSpecifications Timing DiagramsResettiming Reset timing parametersNum Description Min Typ Max Units Sram timing Sram timing parametersNum Description Min Max Unit CS* controlled read wait = Sram readSram burst read CS* controlled read wait = 0, Bcyc = CS controlled write internal and external, wait = Sram writeSram burst write OE* controlled read wait = Sram OE readSram OE burst read WE* controlled write wait = Sram WE writeSram WE burst write Sdram timing parameters Sdram timingSdram read, CAS latency = Sdram readActive Read Inhibit Prechg Bterm Sdram burst read Sdram burst read Sdram write Sdram writeSdram burst write Sdram burst writeSdram refresh Sdram load modeFP Dram timing parameters FP Dram timingFast Page read FP Dram readFast Page burst read FP Dram burst readFast Page write FP Dram writeFast Page burst write FP Dram burst writeFast page refresh Rcyc = FprefreshcyclesCAS3 CAS2 CAS1 CAS0 RF1 RF2 RF3 RF4 RF5 RF8 Ethernet timing parameters Ethernet timingEthernet cam timing Ethernet PHY timingNum Description Min Max Units Jtag arm ice timing diagramJtag timing Jtag arm ice timing parametersJtag bscan timing parameters Jtag bscan timing diagramExternal DMA timing parameters External DMA timingFly-by external DMA Memory-to-memory external DMA 2T SYS Serial internal timing characteristicsSerial external timing characteristics Serial internal/external timingSynchronous serial external clock Synchronous serial internal clockGpio timing diagram Gpio timingGpio timing parameters Page Index CPU Non-Back-to-BackInter-Packet-Gap register FP Dram Portc NET+ARM PORTC0 Receiver interrupts 229 transmitter interrupts Undefined exception 32 Page