Digi NS7520 manual MII Management Address register bit definition, MII PHY device address

E F E c o n f i g u r a t i o n

MII Management Address register

Address: FF80 0428

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							Reserved
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	Reserved				DADR				Reserved				RADR

Register bit assignment

Bits	Access	Mnemonic	Reset	Description
D31:13	N/A	Reserved	N/A	N/A
D12:08	R/W	DADR	0	MII PHY device address
				Represents the 5-bit PHY device address field for
				management cycles. Up to 31 different PHY
				devices can be addressed; address 0 is reserved.
D07:05	N/A	Reserved	N/A	N/A
D04:00	R/W	RADR	0	MII PHY register address
				Represents the 5-bit PHY register address field for
				management cycles. Up to 32 registers within a
				single PHY device can be addressed.

Table 72: MII Management Address register bit definition

1 9 4 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6