G E N m o d u l e r e g i s t e r s

Bits

Access

Mnemonic

Reset

D14

R/W

BUSER

~ADDR

 

 

 

[26]

Description

Enable ARM CPU

Must be set to 0.

When reset, BUSER defaults to the value defined by ADDR26 (see "NS7520 bootstrap initialization" on page 60).

D13

N/A

Reserved

N/A

N/A

 

 

 

 

 

D12

R/W

DMATST

0

DMA module test mode

 

 

 

 

Resets the DMA controller subsystem. Also

 

 

 

 

allows the ARM processor direct access to the

 

 

 

 

internal context RAM found in the DMA controller.

 

 

 

 

When set to 1 (allow unrestricted access),

 

 

 

 

the DMA controller subsystem is held in reset

 

 

 

 

and the ARM processor can access all

 

 

 

 

internal DMA context RAM. This is useful for

 

 

 

 

diagnostic purposes.

 

 

 

 

When set to 0 (test mode disabled), the DMA

 

 

 

 

controller subsystem operates normally. Only

 

 

 

 

the bits in the DMA Control register space

 

 

 

 

can be accessed by the ARM processor.

 

 

 

 

 

D11

R/W

TEALAST

0

Bus interface TEA/LAST configuration

 

 

 

 

This bit can be read or written with a setting of 1

 

 

 

 

or 0, but has no effect on chip functionality.

 

 

 

 

 

D10

R/W

MISALIGN

0

Bus error on misaligned cycles

 

 

 

 

0 Disable misaligned data transfer bus abort

 

 

 

 

generation

 

 

 

 

1 Generate a bus abort during a misaligned

 

 

 

 

transfer

 

 

 

 

When this bit is set to 1, misaligned address

 

 

 

 

transfers cause a data abort to be issued to the

 

 

 

 

offending bus master. A misaligned address

 

 

 

 

transfer is defined as a half word access to an odd

 

 

 

 

byte address boundary, or a full word access to

 

 

 

 

either a half word or byte address boundary.

 

 

 

 

This bit is useful during software debugging to

 

 

 

 

detect misaligned cycles.

 

 

 

 

 

D09:08

N/A

Reserved

N/A

N/A

Table 24: System Control register bit definition

6 6

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

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Image 80
Digi NS7520 Bits Access Mnemonic Reset, Description Enable ARM CPU, DMA module test mode, Bus error on misaligned cycles