S e r i a l C h a n n e l r e g i s t e r s

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

D07

R/C

DCDI

0

Change in DCD interrupt pending

 

 

 

 

Indicates a state change in the EIA data carrier

 

 

 

 

detect signal. Once set, the DCDI field remains

 

 

 

 

set until acknowledged. DCDI is

 

 

 

 

acknowledged by writing a 1 to this same bit

 

 

 

 

position in this register.

 

 

 

 

The DCDI status condition can be programmed

 

 

 

 

to generate an interrupt by setting the related

 

 

 

 

IE bit in Serial Channel Control Register A.

 

 

 

 

 

D06

R/C

RII

0

Change in RI interrupt pending

 

 

 

 

Indicates a state change in the EIA ring

 

 

 

 

indicator signal. Once set, the RII bit remains

 

 

 

 

set until acknowledged. RII is acknowledged

 

 

 

 

by writing a 1 to this same bit position in this

 

 

 

 

register.

 

 

 

 

The RII status condition can be programmed to

 

 

 

 

generate an interrupt by setting the related IE

 

 

 

 

bit in Serial Channel Control Register A.

 

 

 

 

 

D05

R/C

DSRI

0

Change in DSR interrupt pending

 

 

 

 

Indicates a state change in the EIA data set

 

 

 

 

ready signal. Once set, the DSRI bit remains

 

 

 

 

set until acknowledged. DSRI is acknowledged

 

 

 

 

by writing a 1 to this same bit position in this

 

 

 

 

register.

 

 

 

 

The DSRI state condition can be programmed

 

 

 

 

to generate an interrupt by setting the related

 

 

 

 

IE bit in Serial Channel Control Register A.

 

 

 

 

 

D04

R/C

CTSI

0

Change in CTS interrupt pending

 

 

 

 

Indicates a state change in the EIA clear to

 

 

 

 

send signal. Once set, the CTSI bit remains set

 

 

 

 

until acknowledged. CTSI is acknowledged by

writing a 1 to this same bit position in this register.

The CTSI state condition can be programmed to generate an interrupt by setting the related IE bit in Serial Channel Control Register A.

Table 89: Serial Channel Status Register A bit definition

2 4 2

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

Page 256
Image 256
Digi NS7520 manual Change in DCD interrupt pending, Change in RI interrupt pending, Change in DSR interrupt pending