S P I m o d e

controlled by a single clock signal; for SPI slave mode, the signal is an input. Information transfer is also qualified with an enable signal input, which is controlled by the SPI master. The SPI enable signal must be active low for data transfer to occur, regardless of the SPI clock signal. The SPI enable function allows for multiple slaves to be addressed individually during a multi-drop configuration.

Signals

The GEN module must be configured appropriately to allow the SPI interface signals to interface with the PORTA and PORTC GPIO pins (see "PORTA Configuration register" on page 74 and "PORTC Configuration register" on page 77).

Configuration

The SER module must be configured properly to operate in either master or slave mode. For slave mode operation, the MODE field in Serial Channel Control Register B must be set to 11 before the CE field in Serial Channel Control Register A is set to 1.

Use this suggested configuration order for SPI slave mode:

1Reset the serial port by writing a 0 to Serial Channel Control Register a.

2Configure the Serial Channel Bit-Rate register, as shown:

EBIT: 1 for enable

TMODE: 1 for 1x mode

RXSRC: 1 for external;

TXSRC: 1 for external;

RXEXT: 0 for disable

TXEXT: 0 for disable

CLKMUX: n/a (external timing source)

TXCINV: 0 for normal

RXCINV: 0 for normal

N: n/a (external timing source)

3Configure the buffer GAP timer, if you want. The buffer GAP timer terminates a DMA transfer at a programmable interval from the time the first character is received. (See "Serial Channel 1, 2 Receive Buffer Gap Timer," beginning on page 255, for more information).

4Configure the character GAP timer, if you want. The character GAP timer terminates a DMA transfer if the time between the receipt of two characters

2 2 0

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

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Digi NS7520 manual Signals