S e r i a l C o n t r o l l e r M o d u l e

 

 

 

 

 

 

 

 

 

 

 

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

 

 

D03

R

TRDY

0

Transmit register empty interrupt pending

 

 

 

 

Indicates data can be written to the FIFO Data

 

 

 

 

register. TRDY typically is used only in

 

 

 

 

interrupt-driven applications; it is not used for

 

 

 

 

DMA operation. The TRDY status condition

 

 

 

 

can be programmed to generate an interrupt

 

 

 

 

by setting the related IE bit in Serial Channel

 

 

 

 

Control Register A.

 

 

 

 

TRDY is never active while the TBC bit is

 

 

 

 

active. TBC must be acknowledged to activate

 

 

 

 

the TRDY bit. When the transmitter is

 

 

 

 

configured to operate in DMA mode, the

 

 

 

 

interlock between TBC and TRDY is handled

 

 

 

 

automatically in hardware.

 

 

 

 

 

 

D02

R

THALF

0

Transmit FIFO half-empty interrupt pending

 

 

 

 

Indicates that the transmit data FIFO contains

 

 

 

 

room for at least 16 bytes. The THALF field

 

 

 

 

typically is used only in interrupt-driven

 

 

 

 

applications; it is not used for DMA operation.

 

 

 

 

The THALF status condition can be

 

 

 

 

programmed to generate an interrupt by

 

 

 

 

setting the related IE bit in Serial Channel

 

 

 

 

COntrol Register A.

 

 

 

 

 

 

D01

R/C

TBC

0

Transmit buffer closed interrupt pending

 

 

 

 

Indicates a transmit buffer closed condition.

 

 

 

 

Once set, the TBC bit remains set until

acknowledged. TBC is acknowledged by writing a 1 to this same bit position in this register. The TBC bit is acknowledged automatically by hardware when the transmitter is configured to operate in DMA mode. The TBC status condition can be programmed to generate an interrupt by setting the related IE bit in Serial Channel Control Register A.

Table 89: Serial Channel Status Register A bit definition

w w w . d i g i . c o m

2 4 3

Page 257
Image 257
Digi NS7520 manual Transmit register empty interrupt pending, Transmit Fifo half-empty interrupt pending