Digi manual ARM debug, System clock generation NS7520 clock module

S Y S M o d u l e

ARM debug

The ARM7TDMI core uses a JTAG TAP controller that shares pins with the TAP controller used for 1149.1 JTAG boundary scan testing. To enable the ARM7TDMI TAP controller, {PLLTST_, BISTEN_, and SCANEN_} must be set as shown in "External oscillator mode hardware configuration," beginning on page 51.

System clock generation (NS7520 clock module)

The NS7520 clock module creates the BCLK and FXTAL signals. Both signals are used internally, but BCLK can also be accessed at ball A6 by setting the BCLKD field in the System Control register to 0 (see "System Control register," beginning on page 63).

BCLK functions as the system clock and provides the majority of the NS7520’s timing.

FXTAL provides the timing for the DRAM refresh counter, can be selected instead of BCLK to provide timing for the watchdog timer, the two internal timers, and the Serial module.

External oscillator vs. internal PLL circuit

The clock module uses either an external oscillator or the internal PLL circuit to produce the BCLK and FXTAL signals. When using an external oscillator, the minimum high/low time on XTALA1 is 4.5ns.

The PLLTST, BISTEN, and SCANEN signals work together to choose between using the external oscillator or the internal PLL circuit in the boundary scan or JTAG debugger modes, as shown:

PLLTST	BISTEN	SCANEN	FUNCTION
0	0	0	N/A
0	0	1	N/A
0	1	0	N/A
0	1	1	External oscillator, boundary scan

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