T i m i n g D i a g r a m s

SDRAM read

SDRAM read, CAS latency = 2

T1 prechg

BCLK TA* (Note-5)

TEA*/LAST* (Note-5)

PortA2/AMUX

6

Non-muxed address

35

Muxed address

36

BE[3:0]* (DQM)

read D[31:0]

27

CS[4:0]*

34

CAS3* (RAS)

CAS2* (CAS)

34

CAS1* (WE)

CAS0* (A10/AP)

12

RW*

active

read

nop

T2

inhibit

T1

bterm

inhibit

 

 

 

30

30

 

 

 

 

31

31

 

 

37

37

 

 

 

 

35

 

 

 

 

 

 

 

 

36

 

 

 

 

10

11

 

 

 

 

 

 

 

 

 

 

27

 

 

34

 

 

 

 

 

34

34

 

 

 

34

 

 

34

34

 

34

34

34

 

 

 

A10

 

 

 

 

 

Notes:

1Port size determines which byte enable signals are active:

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

2The precharge and/or active commands are not always present. These commands depend on the address of the previous SDRAM access.

3If CAS latency = 3, 2 NOPs occur between the read and burst terminate commands.

4If CAS latency = 3, 3 inhibits occur after burst terminate.

5The TA* and TEA*/LAST signals are for reference only.

2 8 2

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

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Image 296
Digi NS7520 manual Sdram read, CAS latency =