F P / E D O D R A M c o n t r o l l e r

Normal and burst (FP/EDO) cycles

Programmable wait states for normal (also first cycle ion burst access) and burst cycles

Programmable base address and chip select size

Single cycle read/write

Figure 9 shows FP DRAM normal read and write cycles.

T1 TW TW T2

T1 TW TW T2

T1 TW

BCLK

ADDR

R/W_

RAS_

DADDR

CAS_

WE_

OE_

DATA

TA_

FP DRAM Write

FP DRAM Read

Figure 9: Normal FP DRAM bus cycles

All DRAM cycles must operate a minimum of 1 wait state. (If the controller is programmed for 0 wait states, operation is unpredictable). A single wait state DRAM cycle requires the DRAM devices to tolerate a single BCLK cycle for RAS precharge and CAS access timing.

The CAS_ signal is deasserted on the rising edge in which TA_ is recognized.

The RAS_ signal is deasserted on the falling edge of BCLK after CAS_ is asserted.

Important: You cannot set the PS field to 2’b11 for FP DRAM.

1 1 0

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

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Digi NS7520 manual Normal FP Dram bus cycles, FP Dram Write FP Dram Read