Digi NS7520 manual Buffer descriptor bit definitions, Bit Description

D M A M o d u l e

Buffer descriptor bit definitions

Bit Description

W Wrap bit.

When set (W=1), tells the DMA controller that this is the last buffer descriptor within the continuous list of descriptors. The next buffer descriptor is found using the initial DMA channel buffer descriptor pointer.

When not set (W=0), the next buffer descriptor is found using an offset from the current buffer descriptor; that is, the DMA channel continues to address buffer descriptors until it finds a descriptor with W=1 or reaches a 1024-byte boundary.

IWhen set, tells the DMA controller to issue an interrupt to the CPU when the buffer is closed because of normal channel completion. The interrupt occurs regardless of the normal completion interrupt enable configuration for the DMA channel.

LWhen set, tells the DMA controller that this buffer descriptor is the last descriptor and completes an entire message frame. The DMA controller uses this bit to signal the peripheral. Use this bit when multiple descriptors are chained together to form a data frame.

FFor fly-by operations, when set, indicates that the buffer is full. A DMA channel sets this bit after filling a buffer and clears the bit after emptying a buffer. A DMA channel does not try to fill a buffer when the F bit is set, nor does it try to empty a buffer when the F bit is not set. When the F bit is modified by firmware, the firmware driver must write to the DMA Status/Interrupt Enable register to activate an idle DMA channel (see "DMA Status/Interrupt Enable register," beginning on page 142). If a DMA channel encounters a descriptor where F indicates it cannot move data, a maskable interrupt is generated.

For memory-to-memory operations, the F bit must be set to 1 to begin DMA operation.

Table 47: Buffer descriptor bit definitions

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