S D R A M

SDRAM read cycles

Figure 11 and Figure 12 provide timing examples for SDRAM normal and burst reads, respectively, with WAIT and BCYC configured with a value of 0.

precharge

activate

read

bstop

BCLK

 

 

 

TS_

 

 

 

RW_

 

 

 

BE[3:0]

 

 

 

D[31:0]

 

 

 

CS[7:0]_

One Valid Per Cycle

 

CAS3_(RAS_)

CAS2_(CAS_)

CAS1_(WE_)

A[13:0]

AMUX

TA_ {output}

TEA_(LAST_) {output}

TA_ {input}

TEA_(LAST_) {input}

Figure 11: SDRAM normal read

1 2 0

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

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Image 134
Digi NS7520 manual Sdram read cycles, Sdram normal read