E l e c t r i c a l C h a r a c t e r i s t i c s

Fly-by external DMA

 

 

 

T1

TW

T2

BCLK

 

 

 

Mem signals (Note-1)

 

 

 

 

 

 

71

 

 

 

70

DREQ*

 

 

 

 

72

 

72

DACK*

 

 

 

 

75

 

75

DONE* (output)

 

 

 

 

 

 

74

 

 

 

73

DONE* (input)

Note2

 

 

Notes:

1The memory signals are data[31:0], addr[27:0], BE[3:0], CS/RAS[4:0], CAS[3:0], RW, OE*. WE*, and PORTC3/AMUX. The timing of these signals depends on how the memory is configured (Sync SRAM, Async SRAM, FP DRAM, or SDRAM).

2The DONE* signal works as an input only when the DMA channel is configured as fly-by write.

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Digi NS7520 manual Fly-by external DMA