E t h e r n e t M o d u l e

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

D06

R

TXDEF

0

Transmit packet deferred

 

 

 

 

Set to 1 to indicate that the last successfully

 

 

 

 

transmitted Ethernet packet encountered a

 

 

 

 

deferral. Transmission was delayed because the

 

 

 

 

Ethernet medium was busy when trying to send

 

 

 

 

the first transmission.

 

 

 

 

When this bit is set (instead of TXOK or any of the

 

 

 

 

TX abort bits), the transmitter tries to resend the

 

 

 

 

packet. This process continues until the packet is

 

 

 

 

transmitted successfully or an abort condition is

 

 

 

 

detected. A change in transmit error bits can be

 

 

 

 

determined only by polling.

 

 

 

 

 

D05

R

TXCRC

0

Transmit CRC error

 

 

 

 

Set to 1 to indicate that the last successfully

 

 

 

 

transmitted Ethernet packet had an embedded CRC

 

 

 

 

error. This condition occurs only when the CRCEN

 

 

 

 

bit in the MAC Configuration register is set to 0.

 

 

 

 

When CRCEN is set to 0, the MAC does not insert

 

 

 

 

a CRC; the MAC expects a precompiled CRC to be

 

 

 

 

contained in the last four bytes of the Ethernet

 

 

 

 

packet. If the MAC finds that the precompiled CRC

 

 

 

 

is incorrect, the MAC sets the TXCRC bit in this

 

 

 

 

(Ethernet Transmit Status) register.

 

 

 

 

When this bit is set (instead of TXOK or any of the

 

 

 

 

TX abort bits), the transmitter tries to resend the

 

 

 

 

packet. This process continues until the packet is

 

 

 

 

transmitted successfully or an abort condition is

 

 

 

 

detected. A change in transmit error bits can be

 

 

 

 

determined only by polling.

 

 

 

 

 

D04

N/A

Not used

0

Always 0.

Table 58: Ethernet Transmit Status register bit definition

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Image 187
Digi NS7520 manual Txdef, Transmit packet deferred, Txcrc, Transmit CRC error