D01

				G E N M o d u l e


Bits	Access	Mnemonic	Reset	Description

D01	R/W	PORTC1	0	The PORTC1 bit position corresponds to an
				interrupt condition sourced by the PORTC1 input.

D00	R/W	PORTC0	0	The PORTC0 bit position corresponds to an
				interrupt condition sourced by the PORTC0 input.

Table 33: Interrupt Enable registers bit definition

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Contents

NS7520 Hardware Reference Page Part number/version 90000353D Release date March Page Contents A p t e r 4 B B u s M o d u l e A p t e r 7 M e m o r y C o n t r o l l e r M o d u l e A p t e r A p t e r 1 0 S e r i a l C o n t r o l l e r M o d u l e D e Who should read this guide About this guide Conventions used in this guide What’s in this guideTo read about See Related documentation Documentation updatesCustomer support For Contact informationPage About the NS7520 Key features and operating modes of the major NS7520 modules NS7520 Features O u t t h e N S 7 5 2 7 5 2 0 F e a t u r e s NS7520 overview NS7520 module block diagram Operating frequency Pinout and Packaging Symbol Min Nom Max NS7520 packaging dimensionsPackaging NS7520 pinout and dimensions NS7520 BGA layout Column Description Pinout detail tables and signal descriptions System bus interface Symbol Pin DescriptionSystem bus interface pinout External bus ADDR6 ADDR7ADDR5 ADDR4 Do not USE System bus interface signal description Signal descriptionsMnemonic Signal Description Chip select controller pinout Chip select controllerBusy Mnemonic Signal Chip select controller signal description Ethernet interface MAC pinout Ethernet interface MAC Ethernet interface MAC signal description CRS COL No connect pins No connect pinsSerial Other Pin Serial channel Signal Description General-purpose I/O PORTA3 Rxda DACK1 RTS PORTC4 RXCB/RIB ResetPORTA2 Dsra Amux DSR Serial signal Gpio signalOther signal Serial channel Other Description Clock generation and reset signal description System clock and resetSystem clock pinout System mode and system reset pinout System mode test supportPlltst Bisten Jtag test ARM debugger ARM debugger signal descriptionJtag test pinout Trst termination Power supply pinout Power supplySignal Pin Description GND Working with the CPU CPU performance ARM Thumb concept Working with ARM exceptions ARM modeARM performance ARM Exception priorities Summary of ARM exceptions Exception vector table Exception vector tableVector Description Address Detail of ARM exceptions Reset exceptionUndefined exception Abort exception SWI exception Firq exception IRQ exception Entering an exception Entering and exiting an exception software actionExiting an exception Exception entry/exit summary Reset UndefException entry/exit by exception type Abort P Firq and IRQ lines Hardware InterruptsInterrupt controller Interrupt sources W . d i g i . c o m Page BBus Module Cycles and BBus arbitration BBus masters and slavesBBus masters and slaves Module Master Slave BBus address decoding Address decodingAddress range Module Page SYS Module Signal mnemonic Signal name Description Signal descriptionJtag support System clock generation NS7520 clock module ARM debugExternal oscillator vs. internal PLL circuit NS7520 clock module block diagram Using the external oscillator External oscillator mode hardware configuration PLL mode hardware configuration Using the PLL circuit PLL mode hardware configuration PLL Settings register Setting the PLL frequency on bootup Setting the PLL frequencyPLL Settings register bit definition Bits Access Mnemonic Reset Description D3109 Reserved MHz A87 A65 A40 ND+1 PLL Settings reg Bits Access Mnemonic Reset DescriptionOutput divider PLL multiplier MHz A87 A65 A40 ND+1 PLL Settings reg Pllcnt PLL Control register bit definitionSysclk frequency MHz ND+1 PLL Settings register Reset circuit sources Address bit Name Description NS7520 bootstrap initialization GEN Module GEN module address configuration Module configurationGEN module hardware initialization Address Register System Control register GEN module registersAddress FFB0 General information Software watchdog enable Bclk output disableSoftware watchdog reset/interrupt select Software watchdog timeout in seconds Enable access to internal chip registers in CPU Bus monitor enableUser mode Description Enable ARM CPU Bits Access Mnemonic ResetDMA module test mode Bus interface TEA/LAST configuration DMA module reset CPU disableTA input synchronizer System Status register Last reset caused by external resetSystem Status register bit definition NS7520 revision ID Last reset caused by PLL update Last reset caused by watchdog timerLast reset caused by software reset Product ID defined by external resistor jumpers Timer Control registers Software Service registerSoftware Service register bit definition Address FFB0 000C Timer enable Timer Control registers bit definitionTimer interrupt enable Timer interrupt mode Timer clock source Timer prescalerInitial timer count Timer Status registers bit definition Timer Status registersTimer interrupt pending Current timer count Porta mode configuration Porta Configuration registerPorta register bit definition Porta data direction Porta configuration Porta ConfigurationAdata Porta data register Inputs PORTA1 Gpio Gpio OUT SER1CTS DONE1OUT PORTA0 SER1SPISENABLEOutputs IN/SER1DCD Portc mode Portc Configuration registerPortc register bit definition Portc data direction Portc configuration Portc configurationCdata Portc data register PORTC1 Gpio Gpio OUT LEVELIRQ1=CDIR1 PORTC0 LEVELIRQ0=CDIR0 PORTC30 Interrupts Address FFB0 0030 / 0034 Interrupt controller registers Interrupt Enable registers bit definition D01 Page Memory Controller Module MEM module pin configuration by memory type Pin configurationMode A2714 A130 CSx About the MEM module Sdram Mode A2714 A130RAS CAS Setting the chip select address range MEM module configurationMemory controller register map Address Mnemonic Register Memory Space Enable Dram refresh Memory Module Configuration registerMmcr bit definition Refresh count value Enable A27 output Enable external address multiplexingRcyc Refresh cycle count Enable A26 output A27 and A26 bit settingsEnable A25 output AMUX2 Chip Select Base Address register bit definition Chip Select Base Address registerBase Base address Peripheral page size Dram configuration modeDram address multiplexer select Dram internal address multiplexer mode External TA configurationBurst memory cycle enable Force Bclk at end of memory cycle Eeprom Write-protect the chip selectValid bit Chip Select Option Register a bit definition Chip Select Option Register aMask Mask Address When DRSEL=1 and DMODE=2’b00 When DRSEL=0When DRSEL=1 and DMODE=2’b01 at full speed Burst access size in beats When DRSEL=1 and DMODE=10Bsize Port size Write cycle mode Read cycle modeOE Ctrl WE Ctrl Chip Select Option Register B bit definition Chip Select Option Register B Sync Static memory Sram controller Sync Write Sync Read Single cycle read/write Async Read Burst cycles NS7520 Dram address multiplexing Using the internal multiplexer000 001 010 011 100 101 110 111 7 5 2 0 D R a M a d d r e s s m u l t i p l e x i n g NS7520 multiplexed address outputs Internal Dram multiplexing ModeDram Using the external multiplexer FP/EDO Dram controller Dram refresh FP Dram Write FP Dram Read Normal FP Dram bus cycles FP Dram burst cycles FP/EDO Dram burst cycles NS7520 Sdram interconnect X32 Sdram configurationX32 Sdram interconnect BA1 X16 Sdram configurationBA0 BA1 Bclk CLK VCC CKE X16 Sdram interconnect NS7520 signal 16M Sdram signal 64M Sdram signalCAS3 RAS CAS2 CAS1 CAS0 Udqm NS7520 signal 16M Sdram signal X8 Sdram configurationsX8 Sdram interconnect Bclk CLK VCC CKE Sdram A10/AP support Sdram command definitions Command definitionsMux mode X32 X16 Command CAS latency Bcyc configuration Bsize configurationMemory timing fields Sdram Burst length Sdram Mode register settings Sdram Mode registerFull Address Field Value Sdram normal read Sdram read cycles Sdram burst read Sdram normal write Sdram write cycles Sdram burst write Example Peripheral page burst size Wait Bcyc Page DMA Module Fly-by operation transfers DMA module DMA fly-by transfers Memory-to-memory operation DMA buffer descriptor DMA buffer descriptor Fly-by mode Buffer descriptor bit definitions Buffer descriptor bit definitionsBit Description Buffer descriptor field definitions Buffer descriptor field definitionsField Description DMA channel assignments Channel Base address DMA channel peripheral Fly-by modeDMA channel assignments Address map DMA channel registersAddress Description Address Description DMA Control register Buffer Descriptor Pointer register DMA operation mode DMA channel enableDMA Control register bit definition Channel abort request Memory-to-memory mode Burst transfer enableBTE Channel request source REQ Source address increment SincDinc Destination address increment Current DMA channel state shown in binary Data operand sizeCurrent DMA channel buffer descriptor index DMA Status/Interrupt Enable register bit definition DMA Status/Interrupt Enable registerError completion interrupt pending Normal completion interrupt pending Normal completion interrupt enable Premature complete interrupt enableError completion interrupt enable Buffer not ready interrupt enable Ethernet transmitter considerations External peripheral DMA support Ethernet receiver considerations External DMA configuration Signal descriptionMemory-to-memory mode Signal Description Hardware needed for external memory-to-memory DMA transfers DMA controller resetPage Ethernet Module Fifo Ethernet front-end EFE EFE transmit processing Transmit and receive FIFOsEFE receive processing DMA Receive buffer descriptor selection External CAM filtering MAC module MAC module block diagram Other modules in the diagram include EFE register map EFE configurationAddress Register Register description Supp MaxfTest Mcfg Address FF80 Ethernet General Control register Egcr bit definitionsErxetx Erxdmaetxdma Erxlngetxwm Erxshtefulld Erxbad Erxregetxreg Erfifohetfifoh Erxbretxbc Ethernet General Control register bit definition Enable transmit DMA Enable transmit FifoDo not set this bit when operating the Ethernet Receiver in interrupt service mode Enable transmit data Fifo half empty interrupt Enable Transmit Data register ready interruptEnable transmit buffer complete interrupt Enable full-duplex operation Invert the transmit clock input MAC software resetPSOS pNA buffer descriptors Insert transmit source address Endec control signal cross-reference Endec mode and NS7520 pinsExternal interface mode Mode field Output based on EFE CSR bit Ethernet General Status register bit definition Ethernet General Status register Egsr bit definitionsRxfdbrxskip Rxregrtxrege Rxfifohtxfifoh Rxbrtxbc Receive register ready Receive Fifo data availableReceive Fifo half full Receive buffer ready Transmit register empty Receive buffer skipTransmit Fifo half empty Transmit buffer complete Ethernet Fifo Data register Endec status signal cross-referenceAddress FF80 0008 / FF80 000C secondary address Writing to the Ethernet Fifo Data register Reading from the Ethernet Fifo Data register Ethernet Fifo Data register bit definition Ethernet Transmit Status registerEthernet Transmit Status register bit definition Fifo data FF80 Broadcast packet transmitted Packet transmitted OKMulticast packet transmitted Transmit abort late collision Transmit abort excessive deferral TxaedTxaec Transmit abort excessive collisions Transmit aborted underrun TxaurTxaj Transmit abort jumbo Txdef Transmit CRC errorTransmit packet deferred Txcrc Txcolc Ethernet Receive Status registerTransmit collision count Receive buffer size in bytes Ethernet Receive Status register bit definitionReceive carrier event previously seen Receive data violation event previously seen Receive packet has dribble bit error Receive packet has CRC errorReceive broadcast packet Receive multicast packet Receive packet is too long Receive packet has code violationReceive packet is too short Rover MAC Configuration RegisterReceive overflow MAC Configuration Register 1 bit definition RX flow control Receive enablePass ALL receive frames MAC Configuration Register 2 bit definition Vlan pad enable Auto detect pad enablePAD/CRC enable CRC enable PAD operation Pad operation table Back-to-Back Inter-Packet-Gap register bit definition Back-to-Back Inter-Packet-Gap registerBack-to-back inter-packet-gap Address FF80 040C Non-Back-to-Back Inter-Packet-Gap registerNon-Back-to-Back Inter-Packet-Gap register bit definition Non back-to-back inter-packet-gap part Collision Window/Collision Retry register bit definition Collision Window/Collision Retry registerCollision window Retransmission maximum Maximum Frame register bit definition Maximum Frame registerMaximum frame length PHY Support register bit assignment PHY Support register Bit mode Enable Jabber protectionTest register Address FF80 041C Test pause Test backpressureShortcut pause quanta MII Management Configuration register bit definition MII Management Configuration registerReset MII management Clock select Scani Clks field settingsScan increment single scan for read data Clks field Sysclk ratio MHz example MII Management Command register bit definition MII Management Command registerAutomatically scan for read data Single scan for read data MII Management Address register bit definition MII Management Address registerMII PHY device address MII PHY register address Address FF80 042C MII Management Write Data registerMII Management Write Data register bit definition MII write data MII Management Read Data register bit definition MII Management Read Data registerMII read data MII Management Indicators register bit definition MII Management Indicators registerRead data not valid Automatically scan for read data in progress Station Address registers Smii Status registerSmii Status register bit definition Station Address Register 1 bit definition Station Address RegisterStation Address Register 2 bit definition Station address octet OCTET3 Station Address Register 3 bit definitionOCTET4 OCTET5 Address FF80 05C0 Station Address Filter registerStation Address Filter register bit definition Multicast hash table entries and bit definitions Register hash tableAddress FF80 05D0 Address FF80 05D4 Address FF80 05DC Address FF80 05D8HT2 bit definition HT3 bit definition Calculating hash table entries W . d i g i . c o m Page W . d i g i . c o m Page Serial Controller Module RTS, CTS, DTR, DSR, DCD, RI Supported features Bit-rate generator Serial port block diagram Serial protocols Uart mode SPI mode Transmit Fifo interface Fifo managementOperating in Endian modes Terminology What’s being written Value Receive Fifo interface Processor interrupts vs. DMA Using DMA Using processor interrupts Signals SPI master modeConfiguration SPI master transmitter SPI master receiver SPI slave mode Signals SPI slave receiver SPI slave transmitter SPI slave mode 0 and 1 two-byte transfer General-purpose I/O configurations Operating Mode Serial Port Maximum Rate ConfigurationSerial port performance N f i g u r a t i o n Serial Channel 1, 2 Control Register a Serial Channel registersAddress FFD0 0000 Serial Channel Control Register a Stick parity Parity enableEven parity select Number of stop bits Remote loopback Enable the transmitter with active CTSLocal loopback General-purpose output 1/General-purpose Data terminal ready active Enable receive DMA requestsRequest-to-send active Receiver interrupt condition Enable transmit DMA requests Receiver interrupt enable bitsReceiver interrupts Transmitter interrupt condition Transmitter interrupts Transmitter interrupt enable bits Address FFD0 0004 Serial Channel 1, 2 Control Register BSerial Channel Control Register B bit definition SCC mode Enable receive character GAP timerRcgt Bitordr Transmit encoding Enable active RTS only while transmittingReceive data encoding Differential Manchester 111. a 1 is Address FFD0 0008 Serial Channel 1, 2 Status Register a Character Match1 Serial Channel Status Register a bit definitionCharacter Match2 Character Match3 Character GAP timer Buffer GAP timerBgap Cgap DCD Current ring indicator stateCurrent data carrier detect state Current data set ready state Receive parity error interrupt pending Receive framing error interrupt pendingReceive break interrupt pending Rrdy Receive overrun interrupt pendingReceive register ready interrupt pending Receive buffer closed interrupt pending Receive Fifo half-full interrupt pendingReceive Fifo full Change in RI interrupt pending Change in DCD interrupt pendingChange in DSR interrupt pending Change in CTS interrupt pending Transmit Fifo half-empty interrupt pending Transmit register empty interrupt pendingTransmit buffer closed interrupt pending Address FFD0 000C / 4C Serial Channel 1, 2 Bit-Rate registersTempty Timing mode Bit-rate generator enableSerial Channel Bit-Rate register bit definition Receive clock source Drive receive clock external Transmit clock sourceDrive transmit clock external BRG input clock ClkmuxTransmit clock invert Receive clock invert If Dpll is not used but you are using If Dpll is not used and you are not usingWhen Dpll is used in the application, Tdcr Receive divide clock rate Rdcr Transmit internal clock source TicsRics Receiver internal clock source Max baudrates with different clock sources With the 18.432MHz crystal using Xtale as the clock sourceNreg 16X @ 55.296MHz With the 18.432MHz crystal using Sysclk as the clock source Serial Channel 1, 2 Fifo registers X1 mode X8 mode X16 modeAddress FFD0 0010 Bit rate examples Address FFD0 0014 Serial Channel 1, 2 Receive Buffer Gap TimerData Data Register diagram and bit assignment Serial Channel 1, 2 Receive Character Gap TimerSerial Channel Receive Buffer Gap Timer bit definition Address FFD0 0018 CT value Serial Channel Receive Character Gap Timer bit definition Serial Channel 1, 2 Receive Match Mask register Serial Channel 1,2 Receive Match registerAddress FFD0 001C / 5C Address FFD0 0020 RMMB1 Serial Channel Receive Match Mask register bit definitionRMMB2 RMMB3Page Electrical Characteristics Recommended operating conditions DC characteristicsRecommended operating thermal conditions Sym Parameter Conditions Min Typ Max Unit Pad pullup and pulldown characteristics Input/Output characteristicsDC characteristics inputs DC characteristics outputs Internal pullup characteristics AC electrical specifications AC characteristicsAbsolute maximum ratings Maximum voltage ratings System loading details Estimated Signal Load pF Device loadsPORTA3, PORTA1, PORTC3, PORTC1 MDC, MDIO, TXEN, TXER, TXD30 Signal Derating ns/pF Oscillator CharacteristicsOutput buffer derating by load capacitance MDC, TXD30, TXER, TXEN, TDO NS7520 TimingSpecifications Timing Diagrams Reset timing parameters ResettimingNum Description Min Typ Max Units Sram timing parameters Sram timingNum Description Min Max Unit CS* controlled read wait = Sram read Sram burst read CS* controlled read wait = 0, Bcyc = CS controlled write internal and external, wait = Sram write Sram burst write OE* controlled read wait = Sram OE read Sram OE burst read WE* controlled write wait = Sram WE write Sram WE burst write Sdram timing parameters Sdram timing Sdram read, CAS latency = Sdram read Active Read Inhibit Prechg Bterm Sdram burst read Sdram burst read Sdram write Sdram write Sdram burst write Sdram burst write Sdram refresh Sdram load mode FP Dram timing parameters FP Dram timing Fast Page read FP Dram read Fast Page burst read FP Dram burst read Fast Page write FP Dram write Fast Page burst write FP Dram burst write Fast page refresh Rcyc = Fprefreshcycles CAS3 CAS2 CAS1 CAS0 RF1 RF2 RF3 RF4 RF5 RF8 Ethernet timing parameters Ethernet timing Ethernet cam timing Ethernet PHY timing Jtag timing Jtag arm ice timing diagramJtag arm ice timing parameters Num Description Min Max Units Jtag bscan timing parameters Jtag bscan timing diagram External DMA timing parameters External DMA timing Fly-by external DMA Memory-to-memory external DMA Serial external timing characteristics Serial internal timing characteristicsSerial internal/external timing 2T SYS Synchronous serial external clock Synchronous serial internal clock Gpio timing Gpio timing diagramGpio timing parameters Page Index CPU Non-Back-to-BackInter-Packet-Gap register FP Dram Portc NET+ARM PORTC0 Receiver interrupts 229 transmitter interrupts Undefined exception 32 Page

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Models: NS7520

Bits

Table 33: Interrupt Enable registers bit definition

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