S e t t i n g t h e P L L f r e q u e n c y

Setting the PLL frequency

Three fields — IS (charge pump current), FS (output divider), and ND (PLL multiplier) — in the PLL Settings register control the behavior of the PLL circuit. You cannot write to the PLL Settings register directly, however; it is configured in one of these ways:

1On bootup, the PLL Settings register is configured by reading the values on address lines A[8:0]. The address lines have internal pullups. The normally high values can be changed to 0 by connecting 2.7K pulldown resistors.

2The PLL Settings register is configured by writing to the PLL Control register. Only the ND field can be reconfigured this way.

PLL Settings register: Setting the PLL frequency on bootup

The PLL Settings register, FFB0 0040, is initialized at bootup by reading address lines A[8:0]. Only the ND field can be changed by writing a new bus speed to the PLLCNT register in the PLL Control register.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

IS

 

FS

 

 

ND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

D31:09

N/A

Reserved

N/

N/A

Table 21: PLL Settings register bit definition

5 4

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

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Image 68
Digi NS7520 manual PLL Settings register Setting the PLL frequency on bootup, PLL Settings register bit definition