Fifo management, Transmit Fifo interface | Digi NS7520 specs

S P I m o d e

Information transfer is also qualified with an enable signal. The SPI enable signal must be active low for data transfer to occur, regardless of the SPI clock signal. The SPI enable function allows multiple slaves to be individually addressed in a multi-drop configuration.

Note: The NS7520 supports only SPI modes 0 and 1. See Figure 25, "SPI master mode 0 and 1 two-byte transfer," on page 219 and Figure 26, "SPI slave mode 0 and 1 two-byte transfer," on page 222 for illustrations.

FIFO management

Data flow between the SPI master/slave interfaces and memory occurs through the FIFO blocks within the SER module. Each serial port provides a 32-byte transmit FIFO and a 32-byte receive FIFO. Both the transmit and receive FIFOs are memory-mapped to the processor address space.

Transmit FIFO interface

The processor can write either 1, 2, or 4 bytes at a time to the transmit FIFO. The number of bytes written is controlled by the data size defined by the ARM processor as shown in these examples:

Terminology	What’s being written	Value

C	Byte using a byte pointer	(char*)0xffd00010=(char)data

C	2 bytes using a short pointer	(short)0xffd00010=(short)data

C	4 bytes using a standard long word	(long)0xffd00010=(long)data
	pointer

Assembler	Byte	STRB instructions

Assembler	Half word	STRH instructions

Assembler	Long word	STR instructions

Operating in Endian modes

Big Endian mode configuration. Transmits first the most significant bytes in the word written to the FIFO. For example, the long word 0x11223344 results in the character 0x11 being transmitted first and 0x44 being transmitted last.

2 1 4

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

Image 228

Digi NS7520 Fifo management, Transmit Fifo interface, Operating in Endian modes, Terminology What’s being written Value

Contents

NS7520 Hardware Reference Page Part number/version 90000353D Release date March Page Contents A p t e r 4 B B u s M o d u l e A p t e r 7 M e m o r y C o n t r o l l e r M o d u l e A p t e r A p t e r 1 0 S e r i a l C o n t r o l l e r M o d u l e D e About this guide Who should read this guide What’s in this guide Conventions used in this guideTo read about See Documentation updates Related documentationCustomer support For Contact informationPage About the NS7520 NS7520 Features Key features and operating modes of the major NS7520 modules O u t t h e N S 7 5 2 7 5 2 0 F e a t u r e s NS7520 module block diagram NS7520 overview Operating frequency Pinout and Packaging NS7520 packaging dimensions Symbol Min Nom MaxPackaging NS7520 pinout and dimensions NS7520 BGA layout Pinout detail tables and signal descriptions Column Description Symbol Pin Description System bus interfaceSystem bus interface pinout External bus ADDR7 ADDR6ADDR5 ADDR4 Do not USE Signal descriptions System bus interface signal descriptionMnemonic Signal Description Chip select controller Chip select controller pinoutBusy Chip select controller signal description Mnemonic Signal Ethernet interface MAC Ethernet interface MAC pinout Ethernet interface MAC signal description COL CRS No connect pins No connect pinsSerial Other Pin Serial channel Signal Description General-purpose I/O RTS PORTC4 RXCB/RIB Reset PORTA3 Rxda DACK1PORTA2 Dsra Amux DSR Gpio signal Serial signalOther signal Serial channel Other Description System clock and reset Clock generation and reset signal descriptionSystem clock pinout System mode test support System mode and system reset pinoutPlltst Bisten ARM debugger signal description Jtag test ARM debuggerJtag test pinout Trst termination Power supply Power supply pinoutSignal Pin Description GND Working with the CPU ARM Thumb concept CPU performance ARM mode Working with ARM exceptionsARM performance ARM Summary of ARM exceptions Exception priorities Exception vector table Exception vector tableVector Description Address Reset exception Detail of ARM exceptionsUndefined exception SWI exception Abort exception IRQ exception Firq exception Entering and exiting an exception software action Entering an exceptionExiting an exception Reset Undef Exception entry/exit summaryException entry/exit by exception type Abort P Hardware Interrupts Firq and IRQ linesInterrupt controller Interrupt sources W . d i g i . c o m Page BBus Module BBus masters and slaves Cycles and BBus arbitrationBBus masters and slaves Module Master Slave Address decoding BBus address decodingAddress range Module Page SYS Module Signal description Signal mnemonic Signal name DescriptionJtag support ARM debug System clock generation NS7520 clock moduleExternal oscillator vs. internal PLL circuit Using the external oscillator NS7520 clock module block diagram External oscillator mode hardware configuration Using the PLL circuit PLL mode hardware configuration PLL mode hardware configuration Setting the PLL frequency PLL Settings register Setting the PLL frequency on bootupPLL Settings register bit definition Bits Access Mnemonic Reset Description D3109 Reserved Bits Access Mnemonic Reset Description MHz A87 A65 A40 ND+1 PLL Settings regOutput divider PLL multiplier MHz A87 A65 A40 ND+1 PLL Settings reg PLL Control register bit definition PllcntSysclk frequency ND+1 PLL Settings register MHz Reset circuit sources NS7520 bootstrap initialization Address bit Name Description GEN Module Module configuration GEN module address configurationGEN module hardware initialization Address Register GEN module registers System Control registerAddress FFB0 General information Bclk output disable Software watchdog enableSoftware watchdog reset/interrupt select Software watchdog timeout in seconds Bus monitor enable Enable access to internal chip registers in CPUUser mode Bits Access Mnemonic Reset Description Enable ARM CPUDMA module test mode Bus interface TEA/LAST configuration CPU disable DMA module resetTA input synchronizer Last reset caused by external reset System Status registerSystem Status register bit definition NS7520 revision ID Last reset caused by watchdog timer Last reset caused by PLL updateLast reset caused by software reset Product ID defined by external resistor jumpers Software Service register Timer Control registersSoftware Service register bit definition Address FFB0 000C Timer Control registers bit definition Timer enableTimer interrupt enable Timer interrupt mode Timer prescaler Timer clock sourceInitial timer count Timer Status registers Timer Status registers bit definitionTimer interrupt pending Current timer count Porta Configuration register Porta mode configurationPorta register bit definition Porta data direction Porta Configuration Porta configurationAdata Porta data register PORTA1 Gpio Gpio OUT SER1CTS DONE1OUT PORTA0 SER1SPISENABLE InputsOutputs IN/SER1DCD Portc Configuration register Portc modePortc register bit definition Portc data direction Portc configuration Portc configurationCdata Portc data register PORTC1 Gpio Gpio OUT LEVELIRQ1=CDIR1 PORTC0 LEVELIRQ0=CDIR0 Interrupts PORTC30 Interrupt controller registers Address FFB0 0030 / 0034 Interrupt Enable registers bit definition D01 Page Memory Controller Module Pin configuration MEM module pin configuration by memory typeMode A2714 A130 CSx About the MEM module Mode A2714 A130 SdramRAS CAS MEM module configuration Setting the chip select address rangeMemory controller register map Address Mnemonic Register Memory Space Memory Module Configuration register Enable Dram refreshMmcr bit definition Refresh count value Enable external address multiplexing Enable A27 outputRcyc Refresh cycle count A27 and A26 bit settings Enable A26 outputEnable A25 output AMUX2 Chip Select Base Address register Chip Select Base Address register bit definitionBase Base address Dram configuration mode Peripheral page sizeDram address multiplexer select External TA configuration Dram internal address multiplexer modeBurst memory cycle enable Force Bclk at end of memory cycle Write-protect the chip select EepromValid bit Chip Select Option Register a Chip Select Option Register a bit definitionMask Mask Address When DRSEL=0 When DRSEL=1 and DMODE=2’b00When DRSEL=1 and DMODE=2’b01 at full speed When DRSEL=1 and DMODE=10 Burst access size in beatsBsize Port size Read cycle mode Write cycle modeOE Ctrl WE Ctrl Chip Select Option Register B Chip Select Option Register B bit definition Static memory Sram controller Sync Single cycle read/write Sync Write Sync Read Burst cycles Async Read Using the internal multiplexer NS7520 Dram address multiplexing000 001 010 011 100 101 110 111 7 5 2 0 D R a M a d d r e s s m u l t i p l e x i n g Internal Dram multiplexing Mode NS7520 multiplexed address outputsDram Using the external multiplexer Dram refresh FP/EDO Dram controller Normal FP Dram bus cycles FP Dram Write FP Dram Read FP/EDO Dram burst cycles FP Dram burst cycles X32 Sdram configuration NS7520 Sdram interconnectX32 Sdram interconnect X16 Sdram configuration BA1BA0 BA1 Bclk CLK VCC CKE NS7520 signal 16M Sdram signal 64M Sdram signal X16 Sdram interconnectCAS3 RAS CAS2 CAS1 CAS0 Udqm X8 Sdram configurations NS7520 signal 16M Sdram signalX8 Sdram interconnect Bclk CLK VCC CKE Sdram A10/AP support Command definitions Sdram command definitionsMux mode X32 X16 Command Bsize configuration CAS latency Bcyc configurationMemory timing fields Sdram Burst length Sdram Mode register Sdram Mode register settingsFull Address Field Value Sdram read cycles Sdram normal read Sdram burst read Sdram write cycles Sdram normal write Sdram burst write Peripheral page burst size Example Wait Bcyc Page DMA Module DMA module Fly-by operation transfers Memory-to-memory operation DMA fly-by transfers DMA buffer descriptor Fly-by mode DMA buffer descriptor Buffer descriptor bit definitions Buffer descriptor bit definitionsBit Description Buffer descriptor field definitions Buffer descriptor field definitionsField Description Channel Base address DMA channel peripheral Fly-by mode DMA channel assignmentsDMA channel assignments DMA channel registers Address mapAddress Description Address Description Buffer Descriptor Pointer register DMA Control register DMA channel enable DMA operation modeDMA Control register bit definition Channel abort request Burst transfer enable Memory-to-memory modeBTE REQ Channel request source Sinc Source address incrementDinc Destination address increment Data operand size Current DMA channel state shown in binaryCurrent DMA channel buffer descriptor index DMA Status/Interrupt Enable register DMA Status/Interrupt Enable register bit definitionError completion interrupt pending Normal completion interrupt pending Premature complete interrupt enable Normal completion interrupt enableError completion interrupt enable Buffer not ready interrupt enable Ethernet transmitter considerations Ethernet receiver considerations External peripheral DMA support Signal description External DMA configurationMemory-to-memory mode Signal Description DMA controller reset Hardware needed for external memory-to-memory DMA transfersPage Ethernet Module Ethernet front-end EFE Fifo Transmit and receive FIFOs EFE transmit processingEFE receive processing Receive buffer descriptor selection DMA External CAM filtering MAC module block diagram MAC module Other modules in the diagram include EFE configuration EFE register mapAddress Register Register description Maxf SuppTest Mcfg Ethernet General Control register Egcr bit definitions Address FF80Erxetx Erxdmaetxdma Erxlngetxwm Erxshtefulld Erxbad Erxregetxreg Erfifohetfifoh Erxbretxbc Ethernet General Control register bit definition Enable transmit Fifo Enable transmit DMADo not set this bit when operating the Ethernet Receiver in interrupt service mode Enable Transmit Data register ready interrupt Enable transmit data Fifo half empty interruptEnable transmit buffer complete interrupt Enable full-duplex operation MAC software reset Invert the transmit clock inputPSOS pNA buffer descriptors Insert transmit source address Endec mode and NS7520 pins Endec control signal cross-referenceExternal interface mode Mode field Output based on EFE CSR bit Ethernet General Status register Egsr bit definitions Ethernet General Status register bit definitionRxfdbrxskip Rxregrtxrege Rxfifohtxfifoh Rxbrtxbc Receive Fifo data available Receive register readyReceive Fifo half full Receive buffer ready Receive buffer skip Transmit register emptyTransmit Fifo half empty Transmit buffer complete Endec status signal cross-reference Ethernet Fifo Data registerAddress FF80 0008 / FF80 000C secondary address Writing to the Ethernet Fifo Data register Reading from the Ethernet Fifo Data register Ethernet Transmit Status register Ethernet Fifo Data register bit definitionEthernet Transmit Status register bit definition Fifo data FF80 Packet transmitted OK Broadcast packet transmittedMulticast packet transmitted Transmit abort late collision Txaed Transmit abort excessive deferralTxaec Transmit abort excessive collisions Txaur Transmit aborted underrunTxaj Transmit abort jumbo Transmit CRC error TxdefTransmit packet deferred Txcrc Ethernet Receive Status register TxcolcTransmit collision count Ethernet Receive Status register bit definition Receive buffer size in bytesReceive carrier event previously seen Receive data violation event previously seen Receive packet has CRC error Receive packet has dribble bit errorReceive broadcast packet Receive multicast packet Receive packet has code violation Receive packet is too longReceive packet is too short MAC Configuration Register RoverReceive overflow MAC Configuration Register 1 bit definition Receive enable RX flow controlPass ALL receive frames MAC Configuration Register 2 bit definition Auto detect pad enable Vlan pad enablePAD/CRC enable CRC enable Pad operation table PAD operation Back-to-Back Inter-Packet-Gap register Back-to-Back Inter-Packet-Gap register bit definitionBack-to-back inter-packet-gap Non-Back-to-Back Inter-Packet-Gap register Address FF80 040CNon-Back-to-Back Inter-Packet-Gap register bit definition Non back-to-back inter-packet-gap part Collision Window/Collision Retry register Collision Window/Collision Retry register bit definitionCollision window Retransmission maximum Maximum Frame register Maximum Frame register bit definitionMaximum frame length PHY Support register PHY Support register bit assignment Enable Jabber protection Bit modeTest register Address FF80 041C Test backpressure Test pauseShortcut pause quanta MII Management Configuration register MII Management Configuration register bit definitionReset MII management Clock select Clks field settings ScaniScan increment single scan for read data Clks field Sysclk ratio MHz example MII Management Command register MII Management Command register bit definitionAutomatically scan for read data Single scan for read data MII Management Address register MII Management Address register bit definitionMII PHY device address MII PHY register address MII Management Write Data register Address FF80 042CMII Management Write Data register bit definition MII write data MII Management Read Data register MII Management Read Data register bit definitionMII read data MII Management Indicators register MII Management Indicators register bit definitionRead data not valid Automatically scan for read data in progress Smii Status register Station Address registersSmii Status register bit definition Station Address Register Station Address Register 1 bit definitionStation Address Register 2 bit definition Station address octet Station Address Register 3 bit definition OCTET3OCTET4 OCTET5 Station Address Filter register Address FF80 05C0Station Address Filter register bit definition Register hash table Multicast hash table entries and bit definitionsAddress FF80 05D0 Address FF80 05D4 Address FF80 05D8 Address FF80 05DCHT2 bit definition HT3 bit definition Calculating hash table entries W . d i g i . c o m Page W . d i g i . c o m Page Serial Controller Module Supported features RTS, CTS, DTR, DSR, DCD, RI Serial port block diagram Bit-rate generator Uart mode Serial protocols SPI mode Fifo management Transmit Fifo interfaceOperating in Endian modes Terminology What’s being written Value Processor interrupts vs. DMA Receive Fifo interface Using processor interrupts Using DMA SPI master mode SignalsConfiguration SPI master transmitter SPI slave mode SPI master receiver Signals SPI slave transmitter SPI slave receiver General-purpose I/O configurations SPI slave mode 0 and 1 two-byte transfer Configuration Operating Mode Serial Port Maximum RateSerial port performance N f i g u r a t i o n Serial Channel registers Serial Channel 1, 2 Control Register aAddress FFD0 0000 Serial Channel Control Register a Parity enable Stick parityEven parity select Number of stop bits Enable the transmitter with active CTS Remote loopbackLocal loopback General-purpose output 1/General-purpose Enable receive DMA requests Data terminal ready activeRequest-to-send active Receiver interrupt condition Receiver interrupt enable bits Enable transmit DMA requestsReceiver interrupts Transmitter interrupt condition Transmitter interrupt enable bits Transmitter interrupts Serial Channel 1, 2 Control Register B Address FFD0 0004Serial Channel Control Register B bit definition Enable receive character GAP timer SCC modeRcgt Bitordr Enable active RTS only while transmitting Transmit encodingReceive data encoding Differential Manchester 111. a 1 is Serial Channel 1, 2 Status Register a Address FFD0 0008 Serial Channel Status Register a bit definition Character Match1Character Match2 Character Match3 Buffer GAP timer Character GAP timerBgap Cgap Current ring indicator state DCDCurrent data carrier detect state Current data set ready state Receive framing error interrupt pending Receive parity error interrupt pendingReceive break interrupt pending Receive overrun interrupt pending RrdyReceive register ready interrupt pending Receive Fifo half-full interrupt pending Receive buffer closed interrupt pendingReceive Fifo full Change in DCD interrupt pending Change in RI interrupt pendingChange in DSR interrupt pending Change in CTS interrupt pending Transmit register empty interrupt pending Transmit Fifo half-empty interrupt pendingTransmit buffer closed interrupt pending Serial Channel 1, 2 Bit-Rate registers Address FFD0 000C / 4CTempty Bit-rate generator enable Timing modeSerial Channel Bit-Rate register bit definition Receive clock source Transmit clock source Drive receive clock externalDrive transmit clock external Clkmux BRG input clockTransmit clock invert Receive clock invert If Dpll is not used and you are not using If Dpll is not used but you are usingWhen Dpll is used in the application, Tdcr Rdcr Receive divide clock rate Tics Transmit internal clock sourceRics Receiver internal clock source With the 18.432MHz crystal using Xtale as the clock source Max baudrates with different clock sourcesNreg With the 18.432MHz crystal using Sysclk as the clock source 16X @ 55.296MHz X1 mode X8 mode X16 mode Serial Channel 1, 2 Fifo registersAddress FFD0 0010 Bit rate examples Serial Channel 1, 2 Receive Buffer Gap Timer Address FFD0 0014Data Data Serial Channel 1, 2 Receive Character Gap Timer Register diagram and bit assignmentSerial Channel Receive Buffer Gap Timer bit definition Address FFD0 0018 Serial Channel Receive Character Gap Timer bit definition CT value Serial Channel 1,2 Receive Match register Serial Channel 1, 2 Receive Match Mask registerAddress FFD0 001C / 5C Address FFD0 0020 Serial Channel Receive Match Mask register bit definition RMMB1RMMB2 RMMB3Page Electrical Characteristics DC characteristics Recommended operating conditionsRecommended operating thermal conditions Sym Parameter Conditions Min Typ Max Unit Input/Output characteristics Pad pullup and pulldown characteristicsDC characteristics inputs DC characteristics outputs Internal pullup characteristics AC characteristics AC electrical specificationsAbsolute maximum ratings Maximum voltage ratings Estimated Signal Load pF Device loads System loading detailsPORTA3, PORTA1, PORTC3, PORTC1 MDC, MDIO, TXEN, TXER, TXD30 Oscillator Characteristics Signal Derating ns/pFOutput buffer derating by load capacitance MDC, TXD30, TXER, TXEN, TDO NS7520 Timing Diagrams TimingSpecifications Resettiming Reset timing parametersNum Description Min Typ Max Units Sram timing Sram timing parametersNum Description Min Max Unit Sram read CS* controlled read wait = Sram burst read CS* controlled read wait = 0, Bcyc = Sram write CS controlled write internal and external, wait = Sram burst write Sram OE read OE* controlled read wait = Sram OE burst read Sram WE write WE* controlled write wait = Sram WE burst write Sdram timing Sdram timing parameters Sdram read Sdram read, CAS latency = Active Read Inhibit Prechg Bterm Sdram burst read Sdram burst read Sdram write Sdram write Sdram burst write Sdram burst write Sdram load mode Sdram refresh FP Dram timing FP Dram timing parameters FP Dram read Fast Page read FP Dram burst read Fast Page burst read FP Dram write Fast Page write FP Dram burst write Fast Page burst write Fprefreshcycles Fast page refresh Rcyc = CAS3 CAS2 CAS1 CAS0 RF1 RF2 RF3 RF4 RF5 RF8 Ethernet timing Ethernet timing parameters Ethernet PHY timing Ethernet cam timing Jtag arm ice timing diagram Jtag timingJtag arm ice timing parameters Num Description Min Max Units Jtag bscan timing diagram Jtag bscan timing parameters External DMA timing External DMA timing parameters Fly-by external DMA Memory-to-memory external DMA Serial internal timing characteristics Serial external timing characteristicsSerial internal/external timing 2T SYS Synchronous serial internal clock Synchronous serial external clock Gpio timing diagram Gpio timingGpio timing parameters Page Index CPU Non-Back-to-BackInter-Packet-Gap register FP Dram Portc NET+ARM PORTC0 Receiver interrupts 229 transmitter interrupts Undefined exception 32 Page