E l e c t r i c a l C h a r a c t e r i s t i c s

SRAM burst read

 

 

 

 

 

 

 

 

 

 

 

CS* controlled, four word (4-2-2-2), burst read (wait = 2, BCYC = 01)

 

T1

TW

TW

T2

TW

T2

TW

T2

TW

T2

Note-1

T1

BCLK

 

 

 

 

 

 

 

 

 

 

 

TA* (Note-4)

 

 

30

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEA*/LAST (Note-4)

 

 

 

 

 

 

 

 

31

31

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

 

 

A[27:0]

 

 

 

 

 

 

 

 

 

 

 

36

 

 

 

 

 

 

 

 

 

36

 

BE[3:0]* (Note-2)

 

 

 

 

 

 

 

 

 

 

 

CS[4:0]*

27

 

 

 

 

 

 

 

 

27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

11

 

 

 

 

 

 

 

read D[31:0]s

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sync OE*

28

 

 

 

 

 

 

 

 

28

 

 

 

 

 

 

 

 

 

 

 

 

CS0OE*

18

 

 

 

 

 

 

 

 

18

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

RW*

 

 

 

 

 

 

 

 

 

 

 

Notes:

1If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock pulses are required for DMA context switching.

2Port size determines which byte enable signals are active:

8-bit port = BE3*

16-bit port = BE[3:0]

32-bit port = BE[3:0]

3The TW cycles are present when the WAIT field is set to 2 or more.

4The TA* and TEA*/LAST signals are for reference only.

w w w . d i g i . c o m

2 7 3

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Digi NS7520 manual Sram burst read