A C c h a r a c t e r i s t i c s

NS7520

 

SDRAM

 

SDRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Buffer

other memory devices

Figure 30: System configuration for specified timing

 

Estimated

 

Signal

load (pF)

Device loads

 

 

 

BCLK

23

Two SDRAMs, 1 clock buffer/

 

 

clock input to PLD

 

 

 

A[27:0], CAS[3:0]_

23

Two SDRAM An, 1 buffer/PLD

 

 

 

CS[4:0]_

13

Two SDRAM CSn, 1 buffer PLD

 

 

 

DATA[31:0]

18

One SDRAM DQ, 1 buffer/PLD

 

 

 

BE*_

19

One SDRAM DQ, 1 buffer/PLD

 

 

 

TS_, TA_, TEA_, BR_, BG_, BUSY_, WE_,

15

1 buffer/PLD

OE_

 

 

 

 

 

PORTA3, PORTA1, PORTC3, PORTC1

15

1 buffer/PLD

(operating external DMA)

 

 

 

 

 

Other PORTA[*] and PORTC[*], TDO

85

Tester load

 

 

 

MDC, MDIO, TXEN, TXER, TXD[3:0]

20

One PHY

 

 

 

Table 100: System loading details

Exceeding the loading shown in Table 100 can result in additional signal delay. The delay can be approximated by derating the output buffer based on the expected load capacitance per the values shown in Table 101.

2 6 6

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

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Image 280
Digi NS7520 manual System loading details, Estimated Signal Load pF Device loads, PORTA3, PORTA1, PORTC3, PORTC1