Digi NS7520 manual Clkmux, BRG input clock, Transmit clock invert

				S e r i a l C o n t r o l l e r M o d u l e
Bits	Access	Mnemonic	Reset	Description
D25:24	R/W	CLKMUX	0	BRG input clock
				00 Input clock defined by FXTALE
				01 Input clock defined by FSYSCLK
				10 Input clock defined by input on OUT1
				11 Input clock defined by input on OUT2
				Controls the bit-rate generator clock source.
				The bit-rate generator can use one of four
				clock source: the external oscillator, the
				internal PLL SYSCLK output, an input signal on
				the OUT1 signal on PORTA/PORTC, or an
				input signal on the OUT2 signal attached to
				PORTC.
				When using either OUT1 or OUT2, the
				PORTA/PORTC port pin must be configured as
				special function input.
D23	R/W	TXCINV	0	Transmit clock invert
				0 Normal; TXD driven on falling edge of TX
				clock

1 Inverted; TXD driven on rising edge of TX clock

Controls the relationship between transmit clock and transmit data.

When set to 0, transmit data changes relative to the high-to-low transition of the transmit clock.

When set to 1, transmit data changes relative to the low-to-high transition of the transmit clock.

Note: When using SPI mode, this bit must be set to zero.

Table 90: Serial Channel Bit-Rate register bit definition

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