Sinc, Source address increment, Dinc | Digi NS7520 guide

D M A c h a n n e l r e g i s t e r s

Bits	Access	Mnemonic	Reset	Description

REQ continued				DMA channels 4/6 interface with an external
				peripheral using handshaking signals multiplexed
				through PORTC.
				When REQ is set to 0 in DMA channel 4 and
				set to 1 in DMA channel 6, DMA channel 6 is
				tied to the external DMA port through PORTC.
				When REQ is set to 1 in DMA channel 4, that
				channel is tied to the external DMA port
				through PORTC, no matter the REQ bit setting
				in DMA channel 6.
				These bits should not be set in any channels other
				than DMA 3, 4, 5, or 6.

D22	N/A	Reserved	N/A	N/A

D21	R/W	SINC_	0	Source address increment
				0 Increment source address pointer
				1 Do not increment source address pointer
				Controls whether the source address pointer is
				incremented after each DMA transfer. The DMA
				controller uses this bit in all modes when referring
				to a memory address. This bit is ignored when the
				source is a fly-by port.

D20	R/W	DINC_	0	Destination address increment
				0 Increment destination address pointer
				1 Do not increment destination address pointer
				Controls whether the destination address pointer is
				incremented after each DMA transfer. The DMA
				controller uses this bit in all modes when referring
				to a memory address. This bit is ignored when the
				destination is a fly-by port.
				For memory-to-memory operation with DINC_=0,
				the data is written to the specified destination
				address and all subsequent data are written are
				written to the specified destination address+4.

D19:18	N/A	Reserved	N/A	N/A

Table 50: DMA Control register bit definition

1 4 0

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

Image 154

Digi NS7520 manual Sinc, Source address increment, Dinc, Destination address increment

Contents

NS7520 Hardware Reference Page Part number/version 90000353D Release date March Page Contents A p t e r 4 B B u s M o d u l e A p t e r 7 M e m o r y C o n t r o l l e r M o d u l e A p t e r A p t e r 1 0 S e r i a l C o n t r o l l e r M o d u l e D e About this guide Who should read this guide Conventions used in this guide What’s in this guideTo read about See Customer support Documentation updatesRelated documentation For Contact informationPage About the NS7520 NS7520 Features Key features and operating modes of the major NS7520 modules O u t t h e N S 7 5 2 7 5 2 0 F e a t u r e s NS7520 module block diagram NS7520 overview Operating frequency Pinout and Packaging Symbol Min Nom Max NS7520 packaging dimensionsPackaging NS7520 pinout and dimensions NS7520 BGA layout Pinout detail tables and signal descriptions Column Description System bus interface pinout Symbol Pin DescriptionSystem bus interface External bus ADDR5 ADDR7ADDR6 ADDR4 Do not USE System bus interface signal description Signal descriptionsMnemonic Signal Description Chip select controller pinout Chip select controllerBusy Chip select controller signal description Mnemonic Signal Ethernet interface MAC Ethernet interface MAC pinout Ethernet interface MAC signal description COL CRS Serial Other Pin Serial channel Signal Description No connect pinsNo connect pins General-purpose I/O PORTA2 Dsra Amux RTS PORTC4 RXCB/RIB ResetPORTA3 Rxda DACK1 DSR Other signal Gpio signalSerial signal Serial channel Other Description Clock generation and reset signal description System clock and resetSystem clock pinout Plltst System mode test supportSystem mode and system reset pinout Bisten Jtag test ARM debugger ARM debugger signal descriptionJtag test pinout Trst termination Signal Pin Description Power supplyPower supply pinout GND Working with the CPU ARM Thumb concept CPU performance ARM performance ARM modeWorking with ARM exceptions ARM Summary of ARM exceptions Exception priorities Exception vector table Exception vector tableVector Description Address Detail of ARM exceptions Reset exceptionUndefined exception SWI exception Abort exception IRQ exception Firq exception Entering an exception Entering and exiting an exception software actionExiting an exception Exception entry/exit by exception type Reset UndefException entry/exit summary Abort P Firq and IRQ lines Hardware InterruptsInterrupt controller Interrupt sources W . d i g i . c o m Page BBus Module BBus masters and slaves BBus masters and slavesCycles and BBus arbitration Module Master Slave BBus address decoding Address decodingAddress range Module Page SYS Module Signal mnemonic Signal name Description Signal descriptionJtag support System clock generation NS7520 clock module ARM debugExternal oscillator vs. internal PLL circuit Using the external oscillator NS7520 clock module block diagram External oscillator mode hardware configuration Using the PLL circuit PLL mode hardware configuration PLL mode hardware configuration PLL Settings register bit definition Setting the PLL frequencyPLL Settings register Setting the PLL frequency on bootup Bits Access Mnemonic Reset Description D3109 Reserved Output divider Bits Access Mnemonic Reset DescriptionMHz A87 A65 A40 ND+1 PLL Settings reg PLL multiplier MHz A87 A65 A40 ND+1 PLL Settings reg Pllcnt PLL Control register bit definitionSysclk frequency ND+1 PLL Settings register MHz Reset circuit sources NS7520 bootstrap initialization Address bit Name Description GEN Module GEN module hardware initialization Module configurationGEN module address configuration Address Register Address FFB0 GEN module registersSystem Control register General information Software watchdog reset/interrupt select Bclk output disableSoftware watchdog enable Software watchdog timeout in seconds Enable access to internal chip registers in CPU Bus monitor enableUser mode DMA module test mode Bits Access Mnemonic ResetDescription Enable ARM CPU Bus interface TEA/LAST configuration DMA module reset CPU disableTA input synchronizer System Status register bit definition Last reset caused by external resetSystem Status register NS7520 revision ID Last reset caused by software reset Last reset caused by watchdog timerLast reset caused by PLL update Product ID defined by external resistor jumpers Software Service register bit definition Software Service registerTimer Control registers Address FFB0 000C Timer interrupt enable Timer Control registers bit definitionTimer enable Timer interrupt mode Timer clock source Timer prescalerInitial timer count Timer interrupt pending Timer Status registersTimer Status registers bit definition Current timer count Porta register bit definition Porta Configuration registerPorta mode configuration Porta data direction Adata Porta ConfigurationPorta configuration Porta data register Outputs PORTA1 Gpio Gpio OUT SER1CTS DONE1OUT PORTA0 SER1SPISENABLEInputs IN/SER1DCD Portc register bit definition Portc Configuration registerPortc mode Portc data direction Cdata Portc configurationPortc configuration Portc data register PORTC1 Gpio Gpio OUT LEVELIRQ1=CDIR1 PORTC0 LEVELIRQ0=CDIR0 Interrupts PORTC30 Interrupt controller registers Address FFB0 0030 / 0034 Interrupt Enable registers bit definition D01 Page Memory Controller Module Mode A2714 A130 CSx Pin configurationMEM module pin configuration by memory type About the MEM module Sdram Mode A2714 A130RAS CAS Memory controller register map MEM module configurationSetting the chip select address range Address Mnemonic Register Memory Space Mmcr bit definition Memory Module Configuration registerEnable Dram refresh Refresh count value Rcyc Enable external address multiplexingEnable A27 output Refresh cycle count Enable A25 output A27 and A26 bit settingsEnable A26 output AMUX2 Base Chip Select Base Address registerChip Select Base Address register bit definition Base address Peripheral page size Dram configuration modeDram address multiplexer select Burst memory cycle enable External TA configurationDram internal address multiplexer mode Force Bclk at end of memory cycle Eeprom Write-protect the chip selectValid bit Mask Chip Select Option Register aChip Select Option Register a bit definition Mask Address When DRSEL=1 and DMODE=2’b00 When DRSEL=0When DRSEL=1 and DMODE=2’b01 at full speed Bsize When DRSEL=1 and DMODE=10Burst access size in beats Port size OE Ctrl Read cycle modeWrite cycle mode WE Ctrl Chip Select Option Register B Chip Select Option Register B bit definition Static memory Sram controller Sync Single cycle read/write Sync Write Sync Read Burst cycles Async Read NS7520 Dram address multiplexing Using the internal multiplexer000 001 010 011 100 101 110 111 7 5 2 0 D R a M a d d r e s s m u l t i p l e x i n g NS7520 multiplexed address outputs Internal Dram multiplexing ModeDram Using the external multiplexer Dram refresh FP/EDO Dram controller Normal FP Dram bus cycles FP Dram Write FP Dram Read FP/EDO Dram burst cycles FP Dram burst cycles NS7520 Sdram interconnect X32 Sdram configurationX32 Sdram interconnect BA0 X16 Sdram configurationBA1 BA1 Bclk CLK VCC CKE CAS3 RAS CAS2 CAS1 CAS0 NS7520 signal 16M Sdram signal 64M Sdram signalX16 Sdram interconnect Udqm X8 Sdram interconnect X8 Sdram configurationsNS7520 signal 16M Sdram signal Bclk CLK VCC CKE Sdram A10/AP support Mux mode X32 X16 Command definitionsSdram command definitions Command Memory timing fields Sdram Bsize configurationCAS latency Bcyc configuration Burst length Full Sdram Mode registerSdram Mode register settings Address Field Value Sdram read cycles Sdram normal read Sdram burst read Sdram write cycles Sdram normal write Sdram burst write Peripheral page burst size Example Wait Bcyc Page DMA Module DMA module Fly-by operation transfers Memory-to-memory operation DMA fly-by transfers DMA buffer descriptor Fly-by mode DMA buffer descriptor Buffer descriptor bit definitions Buffer descriptor bit definitionsBit Description Buffer descriptor field definitions Buffer descriptor field definitionsField Description DMA channel assignments Channel Base address DMA channel peripheral Fly-by modeDMA channel assignments Address map DMA channel registersAddress Description Address Description Buffer Descriptor Pointer register DMA Control register DMA Control register bit definition DMA channel enableDMA operation mode Channel abort request Memory-to-memory mode Burst transfer enableBTE REQ Channel request source Dinc SincSource address increment Destination address increment Current DMA channel state shown in binary Data operand sizeCurrent DMA channel buffer descriptor index Error completion interrupt pending DMA Status/Interrupt Enable registerDMA Status/Interrupt Enable register bit definition Normal completion interrupt pending Error completion interrupt enable Premature complete interrupt enableNormal completion interrupt enable Buffer not ready interrupt enable Ethernet transmitter considerations Ethernet receiver considerations External peripheral DMA support Memory-to-memory mode Signal descriptionExternal DMA configuration Signal Description DMA controller reset Hardware needed for external memory-to-memory DMA transfersPage Ethernet Module Ethernet front-end EFE Fifo EFE transmit processing Transmit and receive FIFOsEFE receive processing Receive buffer descriptor selection DMA External CAM filtering MAC module block diagram MAC module Other modules in the diagram include EFE register map EFE configurationAddress Register Register description Test MaxfSupp Mcfg Erxetx Erxdmaetxdma Erxlngetxwm Erxshtefulld Erxbad Ethernet General Control register Egcr bit definitionsAddress FF80 Erxregetxreg Erfifohetfifoh Erxbretxbc Ethernet General Control register bit definition Do not set this bit when operating the Ethernet Enable transmit FifoEnable transmit DMA Receiver in interrupt service mode Enable transmit buffer complete interrupt Enable Transmit Data register ready interruptEnable transmit data Fifo half empty interrupt Enable full-duplex operation PSOS pNA buffer descriptors MAC software resetInvert the transmit clock input Insert transmit source address External interface mode Endec mode and NS7520 pinsEndec control signal cross-reference Mode field Output based on EFE CSR bit Ethernet General Status register bit definition Ethernet General Status register Egsr bit definitionsRxfdbrxskip Rxregrtxrege Rxfifohtxfifoh Rxbrtxbc Receive Fifo half full Receive Fifo data availableReceive register ready Receive buffer ready Transmit Fifo half empty Receive buffer skipTransmit register empty Transmit buffer complete Address FF80 0008 / FF80 000C secondary address Endec status signal cross-referenceEthernet Fifo Data register Writing to the Ethernet Fifo Data register Reading from the Ethernet Fifo Data register Ethernet Transmit Status register bit definition Ethernet Transmit Status registerEthernet Fifo Data register bit definition Fifo data FF80 Multicast packet transmitted Packet transmitted OKBroadcast packet transmitted Transmit abort late collision Txaec TxaedTransmit abort excessive deferral Transmit abort excessive collisions Txaj TxaurTransmit aborted underrun Transmit abort jumbo Transmit packet deferred Transmit CRC errorTxdef Txcrc Txcolc Ethernet Receive Status registerTransmit collision count Receive carrier event previously seen Ethernet Receive Status register bit definitionReceive buffer size in bytes Receive data violation event previously seen Receive broadcast packet Receive packet has CRC errorReceive packet has dribble bit error Receive multicast packet Receive packet is too long Receive packet has code violationReceive packet is too short Rover MAC Configuration RegisterReceive overflow MAC Configuration Register 1 bit definition RX flow control Receive enablePass ALL receive frames MAC Configuration Register 2 bit definition PAD/CRC enable Auto detect pad enableVlan pad enable CRC enable Pad operation table PAD operation Back-to-Back Inter-Packet-Gap register bit definition Back-to-Back Inter-Packet-Gap registerBack-to-back inter-packet-gap Non-Back-to-Back Inter-Packet-Gap register bit definition Non-Back-to-Back Inter-Packet-Gap registerAddress FF80 040C Non back-to-back inter-packet-gap part Collision window Collision Window/Collision Retry registerCollision Window/Collision Retry register bit definition Retransmission maximum Maximum Frame register bit definition Maximum Frame registerMaximum frame length PHY Support register PHY Support register bit assignment Test register Enable Jabber protectionBit mode Address FF80 041C Test pause Test backpressureShortcut pause quanta Reset MII management MII Management Configuration registerMII Management Configuration register bit definition Clock select Scan increment single scan for read data Clks field settingsScani Clks field Sysclk ratio MHz example Automatically scan for read data MII Management Command registerMII Management Command register bit definition Single scan for read data MII PHY device address MII Management Address registerMII Management Address register bit definition MII PHY register address MII Management Write Data register bit definition MII Management Write Data registerAddress FF80 042C MII write data MII Management Read Data register bit definition MII Management Read Data registerMII read data Read data not valid MII Management Indicators registerMII Management Indicators register bit definition Automatically scan for read data in progress Station Address registers Smii Status registerSmii Status register bit definition Station Address Register 2 bit definition Station Address RegisterStation Address Register 1 bit definition Station address octet OCTET4 Station Address Register 3 bit definitionOCTET3 OCTET5 Address FF80 05C0 Station Address Filter registerStation Address Filter register bit definition Address FF80 05D0 Register hash tableMulticast hash table entries and bit definitions Address FF80 05D4 HT2 bit definition Address FF80 05D8Address FF80 05DC HT3 bit definition Calculating hash table entries W . d i g i . c o m Page W . d i g i . c o m Page Serial Controller Module Supported features RTS, CTS, DTR, DSR, DCD, RI Serial port block diagram Bit-rate generator Uart mode Serial protocols SPI mode Operating in Endian modes Fifo managementTransmit Fifo interface Terminology What’s being written Value Processor interrupts vs. DMA Receive Fifo interface Using processor interrupts Using DMA Signals SPI master modeConfiguration SPI master transmitter SPI slave mode SPI master receiver Signals SPI slave transmitter SPI slave receiver General-purpose I/O configurations SPI slave mode 0 and 1 two-byte transfer Operating Mode Serial Port Maximum Rate ConfigurationSerial port performance N f i g u r a t i o n Address FFD0 0000 Serial Channel registersSerial Channel 1, 2 Control Register a Serial Channel Control Register a Even parity select Parity enableStick parity Number of stop bits Local loopback Enable the transmitter with active CTSRemote loopback General-purpose output 1/General-purpose Request-to-send active Enable receive DMA requestsData terminal ready active Receiver interrupt condition Receiver interrupts Receiver interrupt enable bitsEnable transmit DMA requests Transmitter interrupt condition Transmitter interrupt enable bits Transmitter interrupts Address FFD0 0004 Serial Channel 1, 2 Control Register BSerial Channel Control Register B bit definition Rcgt Enable receive character GAP timerSCC mode Bitordr Transmit encoding Enable active RTS only while transmittingReceive data encoding Differential Manchester 111. a 1 is Serial Channel 1, 2 Status Register a Address FFD0 0008 Character Match2 Serial Channel Status Register a bit definitionCharacter Match1 Character Match3 Bgap Buffer GAP timerCharacter GAP timer Cgap Current data carrier detect state Current ring indicator stateDCD Current data set ready state Receive parity error interrupt pending Receive framing error interrupt pendingReceive break interrupt pending Rrdy Receive overrun interrupt pendingReceive register ready interrupt pending Receive buffer closed interrupt pending Receive Fifo half-full interrupt pendingReceive Fifo full Change in DSR interrupt pending Change in DCD interrupt pendingChange in RI interrupt pending Change in CTS interrupt pending Transmit Fifo half-empty interrupt pending Transmit register empty interrupt pendingTransmit buffer closed interrupt pending Address FFD0 000C / 4C Serial Channel 1, 2 Bit-Rate registersTempty Serial Channel Bit-Rate register bit definition Bit-rate generator enableTiming mode Receive clock source Drive receive clock external Transmit clock sourceDrive transmit clock external BRG input clock ClkmuxTransmit clock invert Receive clock invert When Dpll is used in the application, If Dpll is not used and you are not usingIf Dpll is not used but you are using Tdcr Rdcr Receive divide clock rate Rics TicsTransmit internal clock source Receiver internal clock source Max baudrates with different clock sources With the 18.432MHz crystal using Xtale as the clock sourceNreg With the 18.432MHz crystal using Sysclk as the clock source 16X @ 55.296MHz Address FFD0 0010 X1 mode X8 mode X16 modeSerial Channel 1, 2 Fifo registers Bit rate examples Data Serial Channel 1, 2 Receive Buffer Gap TimerAddress FFD0 0014 Data Serial Channel Receive Buffer Gap Timer bit definition Serial Channel 1, 2 Receive Character Gap TimerRegister diagram and bit assignment Address FFD0 0018 Serial Channel Receive Character Gap Timer bit definition CT value Address FFD0 001C / 5C Serial Channel 1,2 Receive Match registerSerial Channel 1, 2 Receive Match Mask register Address FFD0 0020 RMMB2 Serial Channel Receive Match Mask register bit definitionRMMB1 RMMB3Page Electrical Characteristics Recommended operating thermal conditions DC characteristicsRecommended operating conditions Sym Parameter Conditions Min Typ Max Unit DC characteristics inputs Input/Output characteristicsPad pullup and pulldown characteristics DC characteristics outputs Internal pullup characteristics Absolute maximum ratings AC characteristicsAC electrical specifications Maximum voltage ratings PORTA3, PORTA1, PORTC3, PORTC1 Estimated Signal Load pF Device loadsSystem loading details MDC, MDIO, TXEN, TXER, TXD30 Output buffer derating by load capacitance Oscillator CharacteristicsSignal Derating ns/pF MDC, TXD30, TXER, TXEN, TDO NS7520 Timing Diagrams TimingSpecifications Reset timing parameters ResettimingNum Description Min Typ Max Units Sram timing parameters Sram timingNum Description Min Max Unit Sram read CS* controlled read wait = Sram burst read CS* controlled read wait = 0, Bcyc = Sram write CS controlled write internal and external, wait = Sram burst write Sram OE read OE* controlled read wait = Sram OE burst read Sram WE write WE* controlled write wait = Sram WE burst write Sdram timing Sdram timing parameters Sdram read Sdram read, CAS latency = Active Read Inhibit Prechg Bterm Sdram burst read Sdram burst read Sdram write Sdram write Sdram burst write Sdram burst write Sdram load mode Sdram refresh FP Dram timing FP Dram timing parameters FP Dram read Fast Page read FP Dram burst read Fast Page burst read FP Dram write Fast Page write FP Dram burst write Fast Page burst write Fprefreshcycles Fast page refresh Rcyc = CAS3 CAS2 CAS1 CAS0 RF1 RF2 RF3 RF4 RF5 RF8 Ethernet timing Ethernet timing parameters Ethernet PHY timing Ethernet cam timing Jtag arm ice timing parameters Jtag arm ice timing diagramJtag timing Num Description Min Max Units Jtag bscan timing diagram Jtag bscan timing parameters External DMA timing External DMA timing parameters Fly-by external DMA Memory-to-memory external DMA Serial internal/external timing Serial internal timing characteristicsSerial external timing characteristics 2T SYS Synchronous serial internal clock Synchronous serial external clock Gpio timing Gpio timing diagramGpio timing parameters Page Index CPU Non-Back-to-BackInter-Packet-Gap register FP Dram Portc NET+ARM PORTC0 Receiver interrupts 229 transmitter interrupts Undefined exception 32 Page