Digi NS7520 manual Resettiming, Reset timing parameters, Num Description Min Typ Max Units

T i m i n g D i a g r a m s

Reset_timing

From a cold start, RESET_ must be asserted until all power supplies are above their specified thresholds. An additional 8 microseconds is required for oscillator settling time (allow 40ms for crystal startup).

Due to an internal three flip-flop delay on the external RESET_ signal, after the oscillator is settled, RESET_ must be asserted for three periods of the XTALA1 clock in these situations:

Before release of reset after application of power

While valid power is maintained to initiate hot reset (reset while power is at or above specified thresholds)

Before loss of valid power during power outage/power down

The PORTC4 output indicates the reset state of the chip. PORTC4 persists beyond the negation of RESET_ for approximately 512 system clock cycles if the PLL is disabled. When the PLL is enabled, PORTC4 persists beyond the negation of RESET_ to allow for PLL lock for 100 microseconds times the ratio of the VCO to XTALA.

VDD, VCC

1

XTALA1

2

RESET_

3

4

Reset timing parameters

Num	Description	Min	Typ	Max	Units
1	Power valid before reset negated	40			ms
					See note
					following table.
2	Reset asserted after power valid	3			TXTALA1
3	Reset asserted while power valid	3			TXTALA1
4	Reset asserted before power invalid	3			TXTALA1

Note: RESET_ should remain low for at least 40ms after power reaches 3.0V.

2 7 0 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6