E t h e r n e t M o d u l e

MII Management Write Data register

Address: FF80 042C

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MII write data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register bit assignment

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

D31:16

N/A

Reserved

N/A

N/A

 

 

 

 

 

D15:00

R/W

MWTD

N/A

MII write data

 

 

 

 

When this register is written, an MII management

 

 

 

 

write cycle is performed using the 16-bit data

defined in the PHY Address register by the preconfigured PHY device and PHY register addresses. The write operation is completed when the BUSY bit in the MII Indicators register (see page 197) returns to 0.

Table 73: MII Management Write Data register bit definition

w w w . d i g i . c o m

1 9 5

Page 209
Image 209
Digi NS7520 manual Address FF80 042C, MII Management Write Data register bit definition, MII write data