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Digi NS7520 manual Receiver interrupts 229 transmitter interrupts

Models: NS7520

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SDRAM timing 281-288

Serial Channel 1,2 Bit-Rate registers 244 Serial Channel 1,2 Control Register A 225

receiver interrupts 229 transmitter interrupts 230

Serial Channel 1,2 Control Register B 231 Serial Channel 1,2 FIFO registers 254

Serial Channel 1,2 Receive Buffer Gap Timer 255

Serial Channel 1,2 Receive Character Gap Timer 256

Serial Channel 1,2 Receive Match MASK register 258

Serial Channel 1,2 Receive Match register 258

Serial Channel 1,2 Status Register A 235 serial internal/external timing 303-304 serial interrupts 40

serial module 209-259

and bit-rate generator 211 configuration 223 features 210

GPIO configurations 222 protocols 212

receiver interrupt enable bits 229

Serial Channel 1,2 Bit-Rate registers 244

Serial Channel 1,2 Control Register A 225

Serial Channel 1,2 Control Register B 231

Serial Channel 1,2 FIFO registers 254

Serial Channel 1,2 Receive Buffer Gap Timer 255

Serial Channel 1,2 Receive Character Gap Timer 256

Serial Channel 1,2 Receive Match MASK register 258

Serial Channel 1,2 Receive Match register 258

Serial Channel 1,2 Status Register A 235

serial port performance 223 SPI mode 213-222

FIFO management 214 master mode 217-219 receive FIFO interface 215 slave mode 219-222 transmit FIFO interface 214

structure 211

transmitter interrupt enable bits 230 UART mode 212-213

serial port performance 223 serial ports 3

single data transfer instructions 35 SMII Status register 198 software action 37

software reset circuit source 59 Software Service register 70 SPI 213-222

controller features 213 FIFO management 214 master configuration 213 master mode 217-219

configuration 217 receiver 219 signals 217 transmitter 218

slave configuration 213 slave mode 219-222

configuration 220 receiver 221 signals 220 transmitter 221

SRAM controller 102-105 burst cycles 104

I n d e x - 8

Image 328

Digi NS7520 manual Receiver interrupts 229 transmitter interrupts

Contents

NS7520 Hardware Reference Page Part number/version 90000353D Release date March Page Contents A p t e r 4 B B u s M o d u l e A p t e r 7 M e m o r y C o n t r o l l e r M o d u l e A p t e r A p t e r 1 0 S e r i a l C o n t r o l l e r M o d u l e D e About this guide Who should read this guideConventions used in this guide What’s in this guideTo read about See Documentation updates Related documentationCustomer support For Contact informationPage About the NS7520 NS7520 Features Key features and operating modes of the major NS7520 modulesO u t t h e N S 7 5 2 7 5 2 0 F e a t u r e s NS7520 module block diagram NS7520 overviewOperating frequency Pinout and Packaging Symbol Min Nom Max NS7520 packaging dimensionsPackaging NS7520 pinout and dimensions NS7520 BGA layout Pinout detail tables and signal descriptions Column DescriptionSymbol Pin Description System bus interfaceSystem bus interface pinout External busADDR7 ADDR6ADDR5 ADDR4Do not USE System bus interface signal description Signal descriptionsMnemonic Signal Description Chip select controller pinout Chip select controllerBusy Chip select controller signal description Mnemonic SignalEthernet interface MAC Ethernet interface MAC pinoutEthernet interface MAC signal description COL CRSNo connect pins No connect pinsSerial Other Pin Serial channel Signal Description General-purpose I/ORTS PORTC4 RXCB/RIB Reset PORTA3 Rxda DACK1PORTA2 Dsra Amux DSRGpio signal Serial signalOther signal Serial channel Other DescriptionClock generation and reset signal description System clock and resetSystem clock pinout System mode test support System mode and system reset pinoutPlltst BistenJtag test ARM debugger ARM debugger signal descriptionJtag test pinout Trst termination Power supply Power supply pinoutSignal Pin Description GNDWorking with the CPU ARM Thumb concept CPU performanceARM mode Working with ARM exceptionsARM performance ARMSummary of ARM exceptions Exception prioritiesException vector table Exception vector tableVector Description Address Detail of ARM exceptions Reset exceptionUndefined exception SWI exception Abort exceptionIRQ exception Firq exceptionEntering an exception Entering and exiting an exception software actionExiting an exception Reset Undef Exception entry/exit summaryException entry/exit by exception type Abort PFirq and IRQ lines Hardware InterruptsInterrupt controller Interrupt sources W . d i g i . c o m Page BBus Module BBus masters and slaves Cycles and BBus arbitrationBBus masters and slaves Module Master SlaveBBus address decoding Address decodingAddress range Module Page SYS Module Signal mnemonic Signal name Description Signal descriptionJtag support System clock generation NS7520 clock module ARM debugExternal oscillator vs. internal PLL circuit Using the external oscillator NS7520 clock module block diagramExternal oscillator mode hardware configuration Using the PLL circuit PLL mode hardware configurationPLL mode hardware configuration Setting the PLL frequency PLL Settings register Setting the PLL frequency on bootupPLL Settings register bit definition Bits Access Mnemonic Reset Description D3109 ReservedBits Access Mnemonic Reset Description MHz A87 A65 A40 ND+1 PLL Settings regOutput divider PLL multiplierMHz A87 A65 A40 ND+1 PLL Settings reg Pllcnt PLL Control register bit definitionSysclk frequency ND+1 PLL Settings register MHzReset circuit sources NS7520 bootstrap initialization Address bit Name DescriptionGEN Module Module configuration GEN module address configurationGEN module hardware initialization Address RegisterGEN module registers System Control registerAddress FFB0 General informationBclk output disable Software watchdog enableSoftware watchdog reset/interrupt select Software watchdog timeout in secondsEnable access to internal chip registers in CPU Bus monitor enableUser mode Bits Access Mnemonic Reset Description Enable ARM CPUDMA module test mode Bus interface TEA/LAST configurationDMA module reset CPU disableTA input synchronizer Last reset caused by external reset System Status registerSystem Status register bit definition NS7520 revision IDLast reset caused by watchdog timer Last reset caused by PLL updateLast reset caused by software reset Product ID defined by external resistor jumpersSoftware Service register Timer Control registersSoftware Service register bit definition Address FFB0 000CTimer Control registers bit definition Timer enableTimer interrupt enable Timer interrupt modeTimer clock source Timer prescalerInitial timer count Timer Status registers Timer Status registers bit definitionTimer interrupt pending Current timer countPorta Configuration register Porta mode configurationPorta register bit definition Porta data directionPorta Configuration Porta configurationAdata Porta data registerPORTA1 Gpio Gpio OUT SER1CTS DONE1OUT PORTA0 SER1SPISENABLE InputsOutputs IN/SER1DCDPortc Configuration register Portc modePortc register bit definition Portc data directionPortc configuration Portc configurationCdata Portc data registerPORTC1 Gpio Gpio OUT LEVELIRQ1=CDIR1 PORTC0 LEVELIRQ0=CDIR0 Interrupts PORTC30Interrupt controller registers Address FFB0 0030 / 0034Interrupt Enable registers bit definition D01 Page Memory Controller Module Pin configuration MEM module pin configuration by memory typeMode A2714 A130 CSx About the MEM moduleSdram Mode A2714 A130RAS CAS MEM module configuration Setting the chip select address rangeMemory controller register map Address Mnemonic RegisterMemory Space Memory Module Configuration register Enable Dram refreshMmcr bit definition Refresh count valueEnable external address multiplexing Enable A27 outputRcyc Refresh cycle countA27 and A26 bit settings Enable A26 outputEnable A25 output AMUX2Chip Select Base Address register Chip Select Base Address register bit definitionBase Base addressPeripheral page size Dram configuration modeDram address multiplexer select External TA configuration Dram internal address multiplexer modeBurst memory cycle enable Force Bclk at end of memory cycleEeprom Write-protect the chip selectValid bit Chip Select Option Register a Chip Select Option Register a bit definitionMask Mask AddressWhen DRSEL=1 and DMODE=2’b00 When DRSEL=0When DRSEL=1 and DMODE=2’b01 at full speed When DRSEL=1 and DMODE=10 Burst access size in beatsBsize Port sizeRead cycle mode Write cycle modeOE Ctrl WE CtrlChip Select Option Register B Chip Select Option Register B bit definitionStatic memory Sram controller SyncSingle cycle read/write Sync Write Sync ReadBurst cycles Async ReadNS7520 Dram address multiplexing Using the internal multiplexer000 001 010 011 100 101 110 111 7 5 2 0 D R a M a d d r e s s m u l t i p l e x i n g NS7520 multiplexed address outputs Internal Dram multiplexing ModeDram Using the external multiplexer Dram refresh FP/EDO Dram controllerNormal FP Dram bus cycles FP Dram Write FP Dram ReadFP/EDO Dram burst cycles FP Dram burst cyclesNS7520 Sdram interconnect X32 Sdram configurationX32 Sdram interconnect X16 Sdram configuration BA1BA0 BA1 Bclk CLK VCC CKENS7520 signal 16M Sdram signal 64M Sdram signal X16 Sdram interconnectCAS3 RAS CAS2 CAS1 CAS0 UdqmX8 Sdram configurations NS7520 signal 16M Sdram signalX8 Sdram interconnect Bclk CLK VCC CKESdram A10/AP support Command definitions Sdram command definitionsMux mode X32 X16 CommandBsize configuration CAS latency Bcyc configurationMemory timing fields Sdram Burst lengthSdram Mode register Sdram Mode register settingsFull Address Field ValueSdram read cycles Sdram normal readSdram burst read Sdram write cycles Sdram normal writeSdram burst write Peripheral page burst size ExampleWait Bcyc Page DMA Module DMA module Fly-by operation transfersMemory-to-memory operation DMA fly-by transfersDMA buffer descriptor Fly-by mode DMA buffer descriptorBuffer descriptor bit definitions Buffer descriptor bit definitionsBit Description Buffer descriptor field definitions Buffer descriptor field definitionsField Description DMA channel assignments Channel Base address DMA channel peripheral Fly-by modeDMA channel assignments Address map DMA channel registersAddress Description Address Description Buffer Descriptor Pointer register DMA Control registerDMA channel enable DMA operation modeDMA Control register bit definition Channel abort requestMemory-to-memory mode Burst transfer enableBTE REQ Channel request sourceSinc Source address incrementDinc Destination address incrementCurrent DMA channel state shown in binary Data operand sizeCurrent DMA channel buffer descriptor index DMA Status/Interrupt Enable register DMA Status/Interrupt Enable register bit definitionError completion interrupt pending Normal completion interrupt pendingPremature complete interrupt enable Normal completion interrupt enableError completion interrupt enable Buffer not ready interrupt enableEthernet transmitter considerations Ethernet receiver considerations External peripheral DMA supportSignal description External DMA configurationMemory-to-memory mode Signal DescriptionDMA controller reset Hardware needed for external memory-to-memory DMA transfersPage Ethernet Module Ethernet front-end EFE FifoEFE transmit processing Transmit and receive FIFOsEFE receive processing Receive buffer descriptor selection DMAExternal CAM filtering MAC module block diagram MAC moduleOther modules in the diagram include EFE register map EFE configurationAddress Register Register description Maxf SuppTest McfgEthernet General Control register Egcr bit definitions Address FF80Erxetx Erxdmaetxdma Erxlngetxwm Erxshtefulld Erxbad Erxregetxreg Erfifohetfifoh ErxbretxbcEthernet General Control register bit definition Enable transmit Fifo Enable transmit DMADo not set this bit when operating the Ethernet Receiver in interrupt service modeEnable Transmit Data register ready interrupt Enable transmit data Fifo half empty interruptEnable transmit buffer complete interrupt Enable full-duplex operationMAC software reset Invert the transmit clock inputPSOS pNA buffer descriptors Insert transmit source addressEndec mode and NS7520 pins Endec control signal cross-referenceExternal interface mode Mode field Output based on EFE CSR bitEthernet General Status register bit definition Ethernet General Status register Egsr bit definitionsRxfdbrxskip Rxregrtxrege Rxfifohtxfifoh Rxbrtxbc Receive Fifo data available Receive register readyReceive Fifo half full Receive buffer readyReceive buffer skip Transmit register emptyTransmit Fifo half empty Transmit buffer completeEndec status signal cross-reference Ethernet Fifo Data registerAddress FF80 0008 / FF80 000C secondary address Writing to the Ethernet Fifo Data registerReading from the Ethernet Fifo Data register Ethernet Transmit Status register Ethernet Fifo Data register bit definitionEthernet Transmit Status register bit definition Fifo data FF80Packet transmitted OK Broadcast packet transmittedMulticast packet transmitted Transmit abort late collisionTxaed Transmit abort excessive deferralTxaec Transmit abort excessive collisionsTxaur Transmit aborted underrunTxaj Transmit abort jumboTransmit CRC error TxdefTransmit packet deferred TxcrcTxcolc Ethernet Receive Status registerTransmit collision count Ethernet Receive Status register bit definition Receive buffer size in bytesReceive carrier event previously seen Receive data violation event previously seenReceive packet has CRC error Receive packet has dribble bit errorReceive broadcast packet Receive multicast packetReceive packet is too long Receive packet has code violationReceive packet is too short Rover MAC Configuration RegisterReceive overflow MAC Configuration Register 1 bit definition RX flow control Receive enablePass ALL receive frames MAC Configuration Register 2 bit definition Auto detect pad enable Vlan pad enablePAD/CRC enable CRC enablePad operation table PAD operationBack-to-Back Inter-Packet-Gap register bit definition Back-to-Back Inter-Packet-Gap registerBack-to-back inter-packet-gap Non-Back-to-Back Inter-Packet-Gap register Address FF80 040CNon-Back-to-Back Inter-Packet-Gap register bit definition Non back-to-back inter-packet-gap partCollision Window/Collision Retry register Collision Window/Collision Retry register bit definitionCollision window Retransmission maximumMaximum Frame register bit definition Maximum Frame registerMaximum frame length PHY Support register PHY Support register bit assignmentEnable Jabber protection Bit modeTest register Address FF80 041CTest pause Test backpressureShortcut pause quanta MII Management Configuration register MII Management Configuration register bit definitionReset MII management Clock selectClks field settings ScaniScan increment single scan for read data Clks field Sysclk ratio MHz exampleMII Management Command register MII Management Command register bit definitionAutomatically scan for read data Single scan for read dataMII Management Address register MII Management Address register bit definitionMII PHY device address MII PHY register addressMII Management Write Data register Address FF80 042CMII Management Write Data register bit definition MII write dataMII Management Read Data register bit definition MII Management Read Data registerMII read data MII Management Indicators register MII Management Indicators register bit definitionRead data not valid Automatically scan for read data in progressStation Address registers Smii Status registerSmii Status register bit definition Station Address Register Station Address Register 1 bit definitionStation Address Register 2 bit definition Station address octetStation Address Register 3 bit definition OCTET3OCTET4 OCTET5Address FF80 05C0 Station Address Filter registerStation Address Filter register bit definition Register hash table Multicast hash table entries and bit definitionsAddress FF80 05D0 Address FF80 05D4Address FF80 05D8 Address FF80 05DCHT2 bit definition HT3 bit definitionCalculating hash table entries W . d i g i . c o m Page W . d i g i . c o m Page Serial Controller Module Supported features RTS, CTS, DTR, DSR, DCD, RISerial port block diagram Bit-rate generatorUart mode Serial protocolsSPI mode Fifo management Transmit Fifo interfaceOperating in Endian modes Terminology What’s being written ValueProcessor interrupts vs. DMA Receive Fifo interfaceUsing processor interrupts Using DMASignals SPI master modeConfiguration SPI master transmitter SPI slave mode SPI master receiverSignals SPI slave transmitter SPI slave receiverGeneral-purpose I/O configurations SPI slave mode 0 and 1 two-byte transferOperating Mode Serial Port Maximum Rate ConfigurationSerial port performance N f i g u r a t i o n Serial Channel registers Serial Channel 1, 2 Control Register aAddress FFD0 0000 Serial Channel Control Register aParity enable Stick parityEven parity select Number of stop bitsEnable the transmitter with active CTS Remote loopbackLocal loopback General-purpose output 1/General-purposeEnable receive DMA requests Data terminal ready activeRequest-to-send active Receiver interrupt conditionReceiver interrupt enable bits Enable transmit DMA requestsReceiver interrupts Transmitter interrupt conditionTransmitter interrupt enable bits Transmitter interruptsAddress FFD0 0004 Serial Channel 1, 2 Control Register BSerial Channel Control Register B bit definition Enable receive character GAP timer SCC modeRcgt BitordrTransmit encoding Enable active RTS only while transmittingReceive data encoding Differential Manchester 111. a 1 is Serial Channel 1, 2 Status Register a Address FFD0 0008Serial Channel Status Register a bit definition Character Match1Character Match2 Character Match3Buffer GAP timer Character GAP timerBgap CgapCurrent ring indicator state DCDCurrent data carrier detect state Current data set ready stateReceive parity error interrupt pending Receive framing error interrupt pendingReceive break interrupt pending Rrdy Receive overrun interrupt pendingReceive register ready interrupt pending Receive buffer closed interrupt pending Receive Fifo half-full interrupt pendingReceive Fifo full Change in DCD interrupt pending Change in RI interrupt pendingChange in DSR interrupt pending Change in CTS interrupt pendingTransmit Fifo half-empty interrupt pending Transmit register empty interrupt pendingTransmit buffer closed interrupt pending Address FFD0 000C / 4C Serial Channel 1, 2 Bit-Rate registersTempty Bit-rate generator enable Timing modeSerial Channel Bit-Rate register bit definition Receive clock sourceDrive receive clock external Transmit clock sourceDrive transmit clock external BRG input clock ClkmuxTransmit clock invert Receive clock invert If Dpll is not used and you are not using If Dpll is not used but you are usingWhen Dpll is used in the application, TdcrRdcr Receive divide clock rateTics Transmit internal clock sourceRics Receiver internal clock sourceMax baudrates with different clock sources With the 18.432MHz crystal using Xtale as the clock sourceNreg With the 18.432MHz crystal using Sysclk as the clock source 16X @ 55.296MHzX1 mode X8 mode X16 mode Serial Channel 1, 2 Fifo registersAddress FFD0 0010 Bit rate examplesSerial Channel 1, 2 Receive Buffer Gap Timer Address FFD0 0014Data DataSerial Channel 1, 2 Receive Character Gap Timer Register diagram and bit assignmentSerial Channel Receive Buffer Gap Timer bit definition Address FFD0 0018Serial Channel Receive Character Gap Timer bit definition CT valueSerial Channel 1,2 Receive Match register Serial Channel 1, 2 Receive Match Mask registerAddress FFD0 001C / 5C Address FFD0 0020Serial Channel Receive Match Mask register bit definition RMMB1RMMB2 RMMB3Page Electrical Characteristics DC characteristics Recommended operating conditionsRecommended operating thermal conditions Sym Parameter Conditions Min Typ Max UnitInput/Output characteristics Pad pullup and pulldown characteristicsDC characteristics inputs DC characteristics outputsInternal pullup characteristics AC characteristics AC electrical specificationsAbsolute maximum ratings Maximum voltage ratingsEstimated Signal Load pF Device loads System loading detailsPORTA3, PORTA1, PORTC3, PORTC1 MDC, MDIO, TXEN, TXER, TXD30Oscillator Characteristics Signal Derating ns/pFOutput buffer derating by load capacitance MDC, TXD30, TXER, TXEN, TDONS7520 Timing Diagrams TimingSpecificationsReset timing parameters ResettimingNum Description Min Typ Max Units Sram timing parameters Sram timingNum Description Min Max Unit Sram read CS* controlled read wait =Sram burst read CS* controlled read wait = 0, Bcyc = Sram write CS controlled write internal and external, wait =Sram burst write Sram OE read OE* controlled read wait =Sram OE burst read Sram WE write WE* controlled write wait =Sram WE burst write Sdram timing Sdram timing parametersSdram read Sdram read, CAS latency =Active Read Inhibit Prechg Bterm Sdram burst read Sdram burst read Sdram write Sdram writeSdram burst write Sdram burst writeSdram load mode Sdram refreshFP Dram timing FP Dram timing parametersFP Dram read Fast Page readFP Dram burst read Fast Page burst readFP Dram write Fast Page writeFP Dram burst write Fast Page burst writeFprefreshcycles Fast page refresh Rcyc =CAS3 CAS2 CAS1 CAS0 RF1 RF2 RF3 RF4 RF5 RF8 Ethernet timing Ethernet timing parametersEthernet PHY timing Ethernet cam timingJtag arm ice timing diagram Jtag timingJtag arm ice timing parameters Num Description Min Max UnitsJtag bscan timing diagram Jtag bscan timing parametersExternal DMA timing External DMA timing parametersFly-by external DMA Memory-to-memory external DMA Serial internal timing characteristics Serial external timing characteristicsSerial internal/external timing 2T SYSSynchronous serial internal clock Synchronous serial external clockGpio timing Gpio timing diagramGpio timing parameters Page Index CPU Non-Back-to-BackInter-Packet-Gap register FP Dram Portc NET+ARM PORTC0 Receiver interrupts 229 transmitter interrupts Undefined exception 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