Intel 80386 manuals
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194 pages 12.31 Mb
3 i,~, 4 TABLE OF CONTENTS 8 CHAPTER 1 HIGHLIGHTS 15 lJ 2-2 Coprocessor Numeric Registers I I I 10PL I 16 2.2 2.2.1 logical Memory and Addressing Segments 2.2.2 Logical Addresses 2.2.3 Segment and Descriptor Registers I I 17 l 19 "I 2-6 2.3.1 l~. b 1-7 20 2.3.2 Numeric Coprocessor Data Types 2.3.3 Other Instructions 2.3.3.1 Stack Instructions 2.3.3.2 Control Transfer Instructions 21 o 2-8 L -It -.l1 __________ 1L- -------.-1 ____ d~.,...I OJ ..... __________ IIL- ... I o I 22 l' 2-9 ____ l _________________ 11 ... --11 ___ &..1 I .. ~ Q ............ 11--. ... I I I I I ... I 3-4 Descriptor Principal 3-4. Figure 1 I I 30 I I I I :~~~' 31 ~t:~:: 3-6 [ .... I----------+- [~~.I I}~:~~' ,~., I:l'tl'ro J 33 n'-f 3-8 Address Physical to Linear 3-6. Figure .... .... ~ ~ 3.3.4 Virtual Memory :J:: l ~ 34 I :::.-D-EF-IN-E-D-)--------l--~l I 38 n I I 39 t Points 3-14 Entry Protected as Gates 3-10. Figure In it 3.6 Interrupts and Exceptions 40 3.6.1. Interrupt Descriptor Table 41 3.6.2 Debug E){ceptions and Registers 3.7 InpuVOutput 46 CHAPTER 4 ARCHITECTURAL COMPATIBILITY is 4.1 80286 Compatibility 4.2 Real and Virtual 86 Modes 4-1 virtual machine 47 4-2 CHAPTER 5 HARDWARE IMPLEMENTATION 52 -54 [ .. v' .. .. Clock 5.2.2 Data and Address Buses .. t----------. 5-4 5.2.3 Bus Cycle Definition 55 C, [ ~- 59 9-HIGH PERFORMANCE 32-BIT MICROPROCESSOR 62 WITH 69 I I I I I 2.3 2.3.1 2.3.2 2.3.3 70 8086 80386 O. 8086 80386 9 80386 2.3.4 Segment Registers - 71 ---- - - -2.3.5 Segment Descriptor Registers 72 f' 4. :;~~\I 2.3.6 Control Registers ~~---------------y--------------~} 73 I = .0:1 80287/80387 = 2.3.7 System Address Registers ~~~:I 74 I I II 2.3.8 Debug and Test Registers I TEST CONTROL I 2.3.9 Register Accessibility 2.3.10 Compatibility 75 2.4 INSTRUCTION SET 2.4.1 Instruction Set Overview 2.4.2 80386 Instructions Table 2-2b Arithmetic Instructions 76 GENERAL Table 2-2a Data Transfer ADDITION PURPOSE CONVERSION MULTIPLICATION INPUT !OUTPUT DIVISION ADDRESS OBJECT AAD ASCII adjust before division FLAG MANIPULATION LODS Load byte or Word, Dword string Table 2-2d Logical Instructions LOGICALS 77 infef 78 80386 2.5 ADDRESSING MODES 2.5.1 Addressing Modes Overview 2.5.2 Register and Immediate Modes 2.5.3 32-Bit Memory Addressing Modes 79 16 Between Differences 2.5.4 / 81 infef rrrrrrrrl Figure 2-10. 80386 Supported Data ...... 11;1-1--1..1--1_1...... I DO~g~~ \~ ..&.I.II_~\ STRI~I~ Iii I iii I' IIi'rlll'"l'ill iii -'-....1...--1..--1_.1...-1 iii 85 infef 11 80386 17-32 0-255 2.9.4 Non-Maskable Interrupt 2.9.5 Software Interrupts 86 2.9.6 88 o c: u, V: 2.11.1 Self-Test 2.11.2 TLB Testing 80386 89 [] Breakpoint 2.12.1 Instruction 2.12.2 Single-Step Trap 2.12.3 Debug Registers I 90 -I I I I I 91 RW Usage Encoding Causing Breakpoint Li 92 3. REAL MODE ARCHITECTURE 3.1 REAL MODE INTRODUCTION 93 ~J_----+_--'-j ~ 3.2 MEMORY ADDRESSING 4.2 95 ! ! ! ! ! ADDRESSING MECHANISM LlNEAR~ ~ 1 , , I 96 l SEGMENTATION 4.3.1 Segmentation Introduction 4.3.2 Terminology 4.3.3 Descriptor Tables -------------- 97 I 98 r = 99 o. o P 4.3.4.4 100 = 0 TYPE = C, GATE 4.3.4.6 9, 3, 1, 4.3.4.5 TSS DESCRIPTORS 0, = (S DESCRIPTORS LDT TYPE = 2) (5=0, TVPE= B) DESCRIPTORS (S=O, TYPE=4-7, F) 101 lsi .. +4 102 I nil I ~ Figure 410. El(smple Descriptor Selection 4.3.4.10 SEGMENT DESCRIPTOR REGISTER SETTINGS 103 ttl _ ~I~I! ~A~~ _L~~E~ is . 4-11 Figure in For compatiblity with the 8086 architecture, the base is In OOOOFFFFH, fixed at is set to sixteen times the current selector value, the limit and the attributes are fixed so as to indicate the segment is present and fully usable. Real Address Mode, the internal "privilege level" always fixed to the highest level, level 0, so I/O and other privileged opcodes may be executed. __ Y 0 Y B U Y Y Y -N Y 0 Y B U Y Y N W - Y 0 Y B U Y Y When operating 104 ___ 12 J 1 ~:!~~~~E ~ :I~I! ~~s~ L~~E~ Protected Mode, each of these fields are defined Figure 4-12. In --------------------~ _ 11 13 Y - 231630-61 Figure 4-12. Segment Descriptor Caches for Protected Mode (Loaded per Descriptor) inter OOOOFFFFH, 44 for Figure 4-13. Segment Descriptor Caches t J 1 _ ~I~I~ B~~E L~~E~ ~~?~~~~E in fixed at in When operating Figure 4-13. For compatibility with the 8086 architecture, the base is set to sixteen times the current selector value, the limit is to allow trapping of all IOPL-sensitive in- structions and level-a-only instructions. 105 __ -- -o Virtual 8086 Mode within Protected Mode (Segment Limit and Attributes are Fixed) 80386 106 4.4 1/0 > of 4.4.2 Rules Protection s: = 4.4.1 Concepts Privilege 4.4.3 Privilege Levels 107 80386 4.4.4 Privilege Level Transfers p-------------. , , , , , , , , , \~ 109 ----I'~ H r- 11L~~~~ Figure 4-15a. 386 TSS and TSS Registers 4.4.5 Call 110 4.4.6 111 infef 4.4.7 Initialization and Transition to Protected Mode ITI 112 """'" 1 ITI t o 4.4.8 Tools for Building Protected Systems 4.5 PAGING 4.5.1 Paging Concepts 4.5.2 Paging Organization 113 '1: ~ I 'r I I f 115 U = Lookaside Buffer 4.5.5 Paging Operation lulululululululululululululul~I:lpl 116 4.5.6 Operating System Responsibilities 4.6 VIRTUAL 8086 ENVIRONMENT 4.6.1 Executing 8086 Programs 4.6.2 Virtual 8086 Mode Addressing Mechanism In 4.6.3 Paging Virtual Mode 117 WI!! o. 118 a + + Handling 4.6.6 Entering and Leaving Virtual 8086 121 5. FUNCTIONAL DATA 5.1 5.2 INTRODUCTION SIGNAL DESCRIPTION 5.2.1 Introduction 5.2.2 Clock (CLK2) 122 R~~~: through A2 Bus (BEO# Address 5.2.4 through (DO 5.2.3 Data Bus < ~ Vee 031) through BE3#, A31) 5.2.5 Bus Cycle Definition Signals 123 MIIO#, LOCK#) ~1%. 129 W/ V@ ~ Organization 5.3.4 Dynamic Data Bus Sizing intef 5.3.5 Interfacing with 32- and 16-Bit Memories 130 i131 intJ 80386 5.4 5.3.6 Operand Alignment BUS FUNCTIONAL DESCRIPTION 5.4.1 Introduction [~ 132 ----= JllVi . Ib, Ivv, Ib, ' .. li,'\~~; [~my", 134 5.4.2 Address Pipelining 5.4.3 Read and Write Cycles 5.4.3.1 Bus Figure 5-11. Various INTRODUCTION 136 ~~9' Cycles and Idle States with Non-Pipelined Address (zero wait states) / nn rut rut rut rut rut nn. rut 137 -----140 rm --0 --0-- --0-- "--- V V V J.lXX.X) ~ I V ,XXXXY DOO()( )[XXX XXX XXX 'XY 'XI --- --- -V 146 rm rm \f \f V V -\......../ '---/XXXX'Y (j 'X'X"X"X IXXXXI>.. IXXX)(>.. XXXXIY '(IXXXX IXXY /..X)( IXXY IXXY ~ --- 147 rm.. 'I' '\\\ x.xxxr XJ\ ~--cp--- ---- ----- ---- .xxx -rut rt.rL rut 4 5.4.4 Interrupt Acknowledge (INTA) Cycles nJ1. nJ1. nJ1. nJ1. -V V V V V V V V --cp---W/R# 148 I I I I 5.4.5 Halt Indication Cycle 5.4.6 Shutdown Indication Cycle the only signals distinguishing shutdown indication 149 I /'V'I:'?~~~~ 5.5 OTHER FUNCTIONAL DESCRIPTIONS 5.5.1 150 ACK~g~~EDGE~ Bus 5.5.3 Entering and Exiting Hold Acknowledge 5.5.2 Reset During Hold Acknowledge Activity During and Following Reset 152 ..Qja~-4~~~~~~~~~~~~ 5.6 SELF-TEST SIGNATURE 5.7 COMPONENT AND REVISION IDENTIFIERS 153 XXXXXXX> 92 RESET BUSY # should be held stable for B CLK2 periods before and after the CLK2 period in which NOTE ~~~~ --- -~~~~~~~~~~~~I.CI~~~~~~~ 1: 80386 Component Revision 80386 Component Revision Stepping Stepping Name Identifier Identifier Name Identifier Identifier 154 inter 5.8 Software Testing 5.8.1 COPROCESSOR INTERFACING for Coprocessor Presence 155 .... .... Pinout-View PGA Figure 6-1. 80386 vce vee vec 6. 6.1 OOOIP@OO~~lf'O@OO vee and GND connections must be made to multi- ple Vee and Vss pins. Each Vee and Vss must be connected to the appropriate voltage level. GND planes for power distribution and all Vee and Vss In this section, the physical packaging and its con- pins must be the appropriate plane. nections are described detail. NOTE: Pins identified as "N.C." should remain completely 6.2 The 80386 pinout as viewed from the top side of the component is shown by Figure 6-1. Its pinout as viewed from the Pin side of the component is Figure 6-2. vee vce vce .... .... .... .... .... .... .... .... .... 156 o o Pin from Pinout-View Figure 62. 80386 PGA 0 000 000 000 0 00000 000 000 000 000 000 0 0 0 0 000 0 0 0 000 0 0 0 0 0 3 o 0 0 0 0 0 0 0 0 0 0 4 5 0 0 0 0 0 0 0 0 0 0 13 o 0 0 0 0 0 0 0 0 0 0 0 0 0 13 14 Side 158 + CTable 62. in 14 a in The initial 80386 package is a 132-pin ceramic .165(4'189~1 -------1 1------ ':....1_ o 0000,0000 o e o e e 5 0000'10000000 000000000000 0 0 000 00 0 00 00 00 00 00 0 0 0 000 00 0 0 0 ,@@@@ -1 ~ Figure 6-3. 132-Pin Ceramic PGA Package Dimensions 6.3 Package Dimensions and Mounting pin grid array (PGA). Pins of this package are arranged 0.100 inch (2.54mm) centertocenter, x 14 matrix, three rows around. soldertail, surface mount, or wire wrap. Several applicable sockets are listed 159 6.4 infef ~99 o UUU UUl Table 6-3. 80386 PGA Package Thermal __ I ~-------l i i = 1-- for Options Socket Table 6-2. Several 132-Pin PGA (Continued) ~1ii 160 ~ Ii. I 161 7. ELECTRICAL DATA 7.1 INTRODUCTION 7.2 POWER AND GROUNDING 7.2.1 Power Connections 7.2.2 Power Decoupling Recommendations 7.2.3 Resistor Recommendations 7.2.4 Other Connection Recommendations 7.3 162 r-____ 163 intJ 7.5 A.C. SPECIFICATIONS 7.5.1 .... __ 164 intJ ~[Q)W~[RI]~~ = A.C. 7.5.2 Specification Tables = Table 7-4. 80386-16 A.C. Characteristics (Continued) Symbol Parameter 80386-16 80386-16 Min Max 165 3 9 M/IO#, W/R#, M/IO#, W/R#, D/C#, Unit Ref. Notes Figure Notes 80386 ~[Q)W~OO[g OOOIP@OOIMl~'iiO@OO 7.5.3 A.C. Test Loads 166 ~CL 7.5.4 A.C. Timing Waveforms [ 167 [ Figure 74. Input Setup and Hold Timing Figure 75. Output Valid Delay Timing 168 'J @ 231630-43 Figure 76. Output Float Delay and HLDA Valid Delay Timing Figure 77. RESET Setup and Hold Timing, and Internal Phase inter 169 L j::..: -::::; -L:.187 / D d Itm FOR 7.6 DESIGNING USE ------+1'1 I t TO ~ 'y o o o of Figure 7-10. Recommended Orientation o o f ! PL o 231630-76 Figure 7-9. ICE-3S6 Optional Interface Module Clearance Requirements (inches) PI~ ~, 170 rDl 231630-74 Lever-Actuated ZIF Socket for ICE-3S6 Use 8. 171 AND COUNT CLOCK 8.1 80386 INSTRUCTION ENCODING SUMMARY 80386 a e 172 I I I r/ml From Register 3/6 rim From Register 2/2 2/2 2/5 rIm mod Segment to Memory Register 2/2 2/2 2/4 2/4 rim rim ock C ount S et CI 3 6 bl T o ummary I Register/Memory Register sreg3 Register/Memory 3/6 rim I I 3/5 = rim IOPL ** If CPL > IOPL Table 81. 80386 Instruction Set Clock Count Summary (Continued) 173 I I ! 2/7 immediate to Immediate mod to Memory to Register data immediate 217 immediate mod CLOCK COUNT NOTES mod or - ! 4 4 3 3 3 3 reg data b Register reg Register/Memory data 217 80386 (C 113 9-38/12-41 9-22/12-25 9-38/12-41 9-22/12-25 9-38/12-41 9-22/12-25 9-14/12-17 9-38/12-4f 9-38/12-41 9-14/12-17 w a r/ml rim] a 8 1 80386 I ontlnue rIm] rIm] 174 I I 175 I I I OOOOOw w Count ~ w Clock Set Instruction Summary (Continued) I immed Bbit data reg 2 2 Table 8-1. 80386 r/ml r/ml r/ml r/ml r/ml Mcdeor Set Instruction Count Summary (Continued) 176 I I I I I 8'/28" If CPL > IOPL 80386 177 c 10PL s; to I/O If mode_ to the port in virtual 6066 I/O permission allows I/O if t 34+m lunSigned r/ml r/ml r/ml r/ml r/ml + 80386 Instruction Set Cloc k Count S 8-1. Table ummary( 5n Notes: bit map denies permission exception 13 fault occurs; refer clock counts for INT 3 instruction_ If CPL If CPL > 10PL Table 8-1. 80386 Instruction Set Clock Count Summar (Continued) 178 I I I 7+ml r/ml Mode Direct within Segment I la.bit Call Via Gate to Same Privilege Level Call Via to Gate Call Via Gate to Same Privilege Level Call Via or Mode or 8086 Mode 8086 Mode Mode (No Parameters) Different Privilege Level, (x Parameters) 94+4x+m Indirect Intersegment I b 56+m Call Gate to Different Privilege Level, (No Parameters) Gate to Different Privilege Level. (x Parameters) 7+ml T 179 I I I I 8bitdispl I 7 + I I 8bit displ I 7 + I I 8bitdispl I 7 + I I 8bit displ I I I 8bit displ I 7 + I I 8bit displ I 7 + I I 8bitdispl I I I 8bit displ I I I 16bit displ I I I 16bit displ I I 180 I I I I I I 8-bitdispl I I 8-bitdispl I I I I I I I I I I I I I I I Set Clock Count Summary (Continued) I Table 8-1. 80386 Instruction Set Clock Count Summary (Continued) 181 , 80386 a e - (C Privilege Different Trap or Interrupt Via Outot bl I ummaay oun CI S T 8 1 80386 I nstructlon et oc kC tS 182 I type I 37 b I r/ml 183 I 122 T bl a e 8-1. 8 o 61 38 to ummary ount S oc et ontlnue d) Interrupt or Trap Gate to Same Privilege Level 59 I 184 infef 8 I I I I I I clock coprocessor. for information Tn I I 185 infef StCI 124 (C ount 5 t" a e -1. T bl 8 803861 ns rue Ion e oe ummary ! + 80386 8.2 INSTRUCTION ENCODING 8.2.1 186 :z Overview o)~~~\ 187 8.2.2 32-Bit Extensions of 8.2.3 Encoding the Instruction Set Instruction Fields by 188 = rim" rim" byte has rim = 100 and mod = 00,01 or 10. 189 infef
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