Intel 80386 manual Interrupt Acknowledge Inta Cycles, ~--cp--- ----- ----- ----- ----- ~

inter80386

Certain types of 16-bit or 8-bit operands require no adjustment for correct transfer on a 16-bit bus. Those are read or write operands using only the low- er half of the data bus, and write operands using only the upper half of the bus since the 80386 simul- taneously duplicates the write data on the lower half of the data bus. For these patterns of Byte Enables and the R/W# signals, B816# need not be assert- ed at the 80386, allowing NA# to be asserted during the bus cycle if desired.

5.4.4Interrupt Acknowledge (INTA) Cycles

In response to an interrupt request on the INTR in- put when interrupts are enabled, the 80386 performs

two interrupt acknowledge cycles. These bus cycles are similar to read cycles in that bus definition sig- nals define the type of bus activity taking place, and each cycle continues until acknowledged by READY # sampled asserted.

The state of A2 distinguishes the first and second interrupt acknowledge cycles. The byte address driven during the first interrupt acknowledge cycle is

4(A31-A3 low, A2 high, BE3 # -BE1 # high, and BEO# low). The address driven during the second interrupt acknowledge cycle is 0 (A31-A2 low, BE3#-BE1 # high, BEO# low).

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231630-26

Interrupt Vector (0-255) is read on DO-D7 at end of second Interrupt Acknowledge bus cycle.

Because each Interrupt Acknowledge bus cycle is followed by idle bus states. asserting NA # has no practical effect. Choose the approach which is simplest for your system hardware design.

Figure 5-22. Interrupt Acknowledge Cycles

86