Intel 80386 manual Electrical Data, Power and Grounding

inter80386

7. ELECTRICAL DATA	piing capacitors as much as possible. Capacitors
	specifically for PGA packages are also commercially
	available, for the lowest possible inductance.

7.1 INTRODUCTION

The following sections describe recommended elec- trical connections for the 80386, and its electrical specifications.

7.2 POWER AND GROUNDING

7.2.1 Power Connections

The 80386 is implemented in CHMOS III technology and has modest power requirements. However, its high clock frequency and 72 output buffers (address, data, control, and HLDA) can cause power surges as multiple output buffers drive new signal levels simultaneously. For clean on-chip power distribution at high frequency, 20 Vee and 21 Vss pins separate- ly feed functional units of the 80386.

Power and ground connections must be made to all external Vee and GND pins of the 80386. On the circuit board, all Vee pins must be connected on a Vee plane. All VSS pins must be likewise connected on a GND plane.

7.2.2Power Decoupling Recommendations

Liberal decoupling capacitance should be placed near the 80386. The 80386 driving its 32-bit parallel address and data buses at high frequencies can cause transient power surges, particularly when driv- ing large capacitive loads.

Low inductance capacitors and interconnects are recommended for best high frequency electrical per- formance. Inductance can be reduced by shortening circuit board traces between the 80386 and decou-

7.2.3 Resistor Recommendations

The ERROR # and BUSY # inputs have resistor pull- ups of approximately 20 K!l built-in to the 80386 to keep these signals negated when neither 80287 or 80387 are present in the system (or temporarily re- moved from its socket). The BS16# input also has an internal pullup resistor of approximately 20 K!l, and the PEREa input has an internal pulldown resis- tor of approximately 20 K!l.

In typical designs, the external pullup resistors shown in Table 7-1 are recommended. However, a particular design may have reason to adjust the re- sistor values recommended here, or alter the use of pullup resistors in other ways.

7.2.4Other Connection Recommendations

For reliable operation, always connect unused in- puts to an appropriate signal level. N.C. pins should always remain unconnected.

Particularly when not using interrupts or bus hold, (as when first prototyping, perhaps) prevent any chance of spurious activity by connecting these as- sociated inputs to GND:

Pin Signal

B7 INTR

B8 NMI

014 HOLD

If not using address pipelining, pullup 013 NA # to

Vee·

If not using 16-bit bus size, pullup C14 BS16# to

			Vee·
			Pullups in the range of 20 K!l are recommended.
		Table 7·1.Recommended Resistor Pullups to Vee
Pin and Signal		Pullup Value	Purpose
E14	ADS#	20 K!l ±10%	Lightly Pull ADS# Negated
			During 80386 Hold Acknowledge
			States
C10	LOCK #	20 K!l ±10%	Lightly Pull LOCK # Negated
			During 80386 Hold Acknowledge

States

100